summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/util
diff options
context:
space:
mode:
authorJiuyang Liu2021-12-09 10:25:11 +0800
committerGitHub2021-12-09 02:25:11 +0000
commit849d4a0b7f6f7ea056c5280b9d319dadf5225022 (patch)
tree631c2271af185fdacc0cbe22d907afe25c12959d /src/test/scala/chiselTests/util
parent2e2c7c0857bf9f7d0bde75e22f01b5f092d6e33c (diff)
catch None.get in BitPat.apply(x: UInt): BitPat (#2276)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/util')
-rw-r--r--src/test/scala/chiselTests/util/BitPatSpec.scala8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
index 0c83493f..e14b4496 100644
--- a/src/test/scala/chiselTests/util/BitPatSpec.scala
+++ b/src/test/scala/chiselTests/util/BitPatSpec.scala
@@ -28,6 +28,14 @@ class BitPatSpec extends AnyFlatSpec with Matchers {
(BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)")
}
+ it should "throw when BitPat apply to a Hardware" in {
+ intercept[java.lang.IllegalArgumentException]{
+ chisel3.stage.ChiselStage.emitChirrtl(new chisel3.Module {
+ BitPat(chisel3.Reg(chisel3.Bool()))
+ })
+ }
+ }
+
it should "index and return new BitPat" in {
val b = BitPat("b1001???")
b(0) should be(BitPat.dontCare(1))