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Widths are now padded to the maximum width of the inputs.
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38)
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
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Command:
sbt scalafmtAll
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This makes the resulting Verilog from decoding a TruthTable deterministic.
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* replace custom model checker with chiseltest formal verify command
* integration-tests can make use of chiseltest
This is a compromise solution to avoid issues
with binary compatibility breaking changes in chisel3.
* ci: move integration tests into separate job
* run integration tests only for one scala version
* ci: install espresso for integration tests
* Update build.sbt
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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Co-authored-by: Haoran Yuan <sinofp@tuta.io>
Co-authored-by: Boyang Han <yqszxx@gmail.com>
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* implement pla
* implement test for pla
* implement inverter matrix of PLA generator
* fix for review.
Co-authored-by: Boyang Han <yqszxx@gmail.com>
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