diff options
| author | Boyang Han | 2021-06-23 17:37:27 +0800 |
|---|---|---|
| committer | Jiuyang Liu | 2021-06-30 22:07:59 +0800 |
| commit | 1e40c7e2a2fd227c752e4e4dc29925004f790f7d (patch) | |
| tree | 5db9e18736c632bff51595bf1635dd3751eb3154 /src/test/scala/chiselTests/util/experimental | |
| parent | 1bf2d53046bdac65013f2e32f8c087f881a959b8 (diff) | |
Add 7 segment display decoder test case
Diffstat (limited to 'src/test/scala/chiselTests/util/experimental')
| -rw-r--r-- | src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala index a9e56800..5e3be9a6 100644 --- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala +++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala @@ -96,6 +96,24 @@ trait MinimizerSpec extends SMTModelCheckingSpec { ), "caseMultiDefault") } + "case7SegDecoder" should "pass" in { + minimizerTest(TruthTable( + Map( + BitPat("b0000") -> BitPat("b111111001"), + BitPat("b0001") -> BitPat("b011000001"), + BitPat("b0010") -> BitPat("b110110101"), + BitPat("b0011") -> BitPat("b111100101"), + BitPat("b0100") -> BitPat("b011001101"), + BitPat("b0101") -> BitPat("b101101101"), + BitPat("b0110") -> BitPat("b101111101"), + BitPat("b0111") -> BitPat("b111000001"), + BitPat("b1000") -> BitPat("b111111101"), + BitPat("b1001") -> BitPat("b111101101"), + ), + BitPat("b???????10") + ), "case7SegDecoder") + } + // A simple RV32I decode table example "caseRV32I" should "pass" in { val BEQ = "?????????????????000?????1100011" |