| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-01-10 | Apply scalafmt | Jack Koenig | |
| Command: sbt scalafmtAll | |||
| 2021-12-15 | Refactor TruthTable to use Seq (#2217) | Jiuyang Liu | |
| This makes the resulting Verilog from decoding a TruthTable deterministic. | |||
| 2021-09-06 | Test case rework | Boyang Han | |
| 2021-09-06 | Add a test case to demonstrate the bug found in #2112 | Boyang Han | |
| 2021-08-25 | replace custom model checker with chiseltest formal verify command (#2075) | Kevin Laeufer | |
| * replace custom model checker with chiseltest formal verify command * integration-tests can make use of chiseltest This is a compromise solution to avoid issues with binary compatibility breaking changes in chisel3. * ci: move integration tests into separate job * run integration tests only for one scala version * ci: install espresso for integration tests * Update build.sbt Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> | |||
| 2021-07-14 | Espresso Decoder (#1964) | Jiuyang Liu | |
| Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com> | |||
| 2021-06-30 | Add 7 segment display decoder test case | Boyang Han | |
| 2021-06-16 | implement test for qmc | Jiuyang Liu | |
| 2021-06-16 | Add test cases. | Jiuyang Liu | |
| 2021-06-16 | switch to EndToEndSMTBaseSpec | Jiuyang Liu | |
| 2021-06-16 | Add minimized form of test cases | Boyang Han | |
| 2021-06-16 | use z3 formal check minimized circuit and reference model. | Jiuyang Liu | |
| 2021-06-16 | test decode cache. | Jiuyang Liu | |
| 2021-06-16 | TruthTable can merge same inputs now. | Jiuyang Liu | |
| 2021-06-16 | implement TruthTable to represent a decode table. | Jiuyang Liu | |
| 2021-05-20 | Implement PLA (#1912) | Jiuyang Liu | |
| * implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com> | |||
