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This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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* prototype annotating verif constructs
* switch to final class
* name emissions
* moving BaseSim to experimental
* adding name tests
* fixing quotation escapes
* emitting names, but everything has a default name
* only name things with provided/suggested names
* name every BaseSim node
* removing msg, unused imports
* fixing file exist calls
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Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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ChiselStage$ helpers (#1566)
* Add ChiselPhase
* Use ChiselPhase in ChiselStage, remove targets
Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.
* Stop writing to files in ChiselStage$ methods
Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.
* Test that ChiselStage$ methods write no files
Modify existing ChiselStage object method tests to check that no files
are written.
* Expand ChiselStage$ API with more helpers
This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.
Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.
* Add tests of new ChiselStage$ helper methods
* Use ChiselStage object in tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add `check(...)` affordance
* Add assert (renamed from check and fixed)
* Add verification statements
* Move formal to experimental.verification
* Make test use ChiselStage
`generateFirrtl` has been cut from Chisel
* Fix newly introduced style warnings
* Fix some old style warnings for good measure
* Revert "Fix some old style warnings for good measure"
This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890.
* Cut scalastyle comments
* Cut formal delimiter comments
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