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* Promote ChiselEnum user APIs from experimental (#2929)
They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.
Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.
(cherry picked from commit 424e9446f1675fe0168e22bdfbbe85db997376e6)
# Conflicts:
# docs/src/cookbooks/verilog-vs-chisel.md
# docs/src/explanations/chisel-enum.md
* Maintain binary compatbility, use aliases in chisel3 package
* Deprecate the actual classes in chisel3.experimental
* Also fix backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(#2757)
* Add internal methods to maintain binary compatibility
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.
Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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functions (#2124)
* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent
Co-authored-by: Megan Wachs <megan@sifive.com>
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This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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