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path: root/src/test/scala/chiselTests/Reg.scala
AgeCommit message (Expand)Author
2022-01-10Apply scalafmtJack Koenig
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-01-30Add shift register with reset (#439)Stevo
2016-11-21Restyle a lot of test code, mainly with regexducky
2016-10-14Implement a standardized execution scheme for chiselchick
2016-09-29Massive rename of CompileOptions.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-07-25Minimize differences with master.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-08Rename Chisel -> chisel in testsducky
2015-12-06Split internal and FIRRTL packagesducky
2015-11-04Use elaborate for elaboration tests, not executeHenry Cook
2015-10-23Add Scalaland unit tests for Regducky