summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/PrintableSpec.scala
AgeCommit message (Expand)Author
2023-11-23cleanupAditya Naik
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
2022-01-10Apply scalafmtJack Koenig
2021-10-05Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)Megan Wachs
2021-09-23make all verification statements publically available (#2089)Kevin Laeufer
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselSta...Schuyler Eldridge
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
2020-04-13Update scalatest to 3.1.0 (#1394)Jim Lawson
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
2018-07-02Direct to FIRRTL (#829)Jack Koenig
2017-08-17More of the bindings refactor (#635)Richard Lin
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2016-11-21Restyle a lot of test code, mainly with regexducky
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig