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path: root/src/test/scala/chiselTests/Mem.scala
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2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2020-10-22Use Data refs for name prefixing with aggregate elements (#1616)Jack Koenig
* Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
This is necessary to support code that imports an implicit conversion from Int to UInt
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2018-05-23Add test for zero-width Mems. (#821)grebe
2018-03-06Fix SyncReadMem.read; add test (#796)Andrew Waterman
SyncReadMem.read with an enable signal currently only works in compatibility mode, where Wires are implicitly initialized to DontCare. Fix by explicitly assigning DontCare to the Wire. This might fix #775.
2017-12-19Add source info / compile options transforms to Mem accessors (#744)Richard Lin
Fixes #708