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path: root/src/test/scala/chiselTests/Mem.scala
AgeCommit message (Expand)Author
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
2022-01-10Apply scalafmtJack Koenig
2020-10-22Use Data refs for name prefixing with aggregate elements (#1616)Jack Koenig
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2018-05-23Add test for zero-width Mems. (#821)grebe
2018-03-06Fix SyncReadMem.read; add test (#796)Andrew Waterman
2017-12-19Add source info / compile options transforms to Mem accessors (#744)Richard Lin