| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-03-11 | Import memory files inline for Verilog generation (#1805) | Carlos Eduardo |
| 2020-10-01 | Move Chisel3 to SPDX license conventions (#1604) | Chick Markley |
| 2020-09-09 | Fix load memory from file to work with binary (#1583) | HappyQuark |
| 2020-06-22 | Use ChiselStage in Tests | Schuyler Eldridge |
| 2020-04-13 | Update scalatest to 3.1.0 (#1394) | Jim Lawson |
| 2018-08-31 | Support for verilog memory loading. (#840) | Chick Markley |
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index : chiselX | |
| Chisel with SFC compatibility |
| summaryrefslogtreecommitdiff |