| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-10-01 | Move Chisel3 to SPDX license conventions (#1604) | Chick Markley |
| 2019-05-20 | Repackagecore rebase (#1078) | Jim Lawson |
| 2017-02-01 | Move backend compilation utilities (#400) | Jim Lawson |
| 2017-01-10 | Make stop() immediately end simulation for Verilator tests (#434) | Jack Koenig |
| 2016-06-20 | Rename "package", "import", and explicit references to "chisel3". | Jim Lawson |
| 2016-06-08 | Rename Chisel -> chisel in tests | ducky |
| 2016-05-20 | Update BackendCompilationUtilities.verilogToCpp to specify top-module | jackkoenig |
| 2016-03-18 | Only randomize directory names during testing | jackkoenig |
| 2015-12-09 | Refactor testharness generation to create directories and have minimal API | ducky |
| 2015-12-09 | Extend TesterDriver to optionally take in additional Verilog sources | ducky |
| 2015-11-04 | Style fixes for test code, so we can go back down to zero style errors for tests | ducky |
| 2015-11-04 | Remove Parameters library and refactor Driver. | Henry Cook |
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index : chiselX | |
| Chisel with SFC compatibility |
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