chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2019-07-18	Support Analog DontCare bulk-connect (#1056)	Richard Lin
	Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-05-09	Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)	Jack Koenig
	* IO(Analog) fixed for RawModule * Add a Analog Port for RawModule test & spec * Fixes around Module instantiation and ports in AnalogPortRawModuleTest * Shorten Comment * Add Data.isSynthesizable to distinguish SampleElementBinding This helps clarify the notion of being bound but not hardware. Data.topBindingOpt is now used to get the actual top binding, including across SampleElements (eg. in Analog checking that the top is bound to a Port or a Wire) * Fix pretty printing for Vec * Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
2019-01-25	WireDefault instead of WireInit, keep WireInit around (#986)	Martin Schoeberl

2017-08-17	More of the bindings refactor (#635)	Richard Lin
	Rest of the binding refactor
2017-05-11	Scope resources - move them down into chisel3 directory - fixes #549 (#610)	Jim Lawson

2017-04-13	Module Hierarchy Refactor (#469)	Richard Lin

2017-02-08	Add Analog type	Jack Koenig
	Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)