Module Hierarchy Refactor (#469)

1 files changed, 3 insertions, 3 deletions

diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index 576a5a1f..5db9ab53 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.util._
 import chisel3.testers.BasicTester
-import chisel3.experimental.{Analog, attach}
+import chisel3.experimental.{Analog, attach, BaseModule}
 
 // IO for Modules that just connect bus to out
 class AnalogReaderIO extends Bundle {
@@ -19,7 +19,7 @@ class AnalogWriterIO extends Bundle {
 }
 
 trait AnalogReader {
-  self: Module =>
+  self: BaseModule =>
   final val io = self.IO(new AnalogReaderIO)
 }
 
@@ -51,7 +51,7 @@ abstract class AnalogTester extends BasicTester {
   final val writer = Module(new AnalogWriterBlackBox)
   writer.io.in := BusValue
 
-  final def check(reader: Module with AnalogReader): Unit =
+  final def check(reader: BaseModule with AnalogReader): Unit =
     assert(reader.io.out === BusValue)
 }