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Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
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Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
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* Move copyResourceToFile() to BackendCompilationUtilities.
* Move BackendCompilationUtilities into a firrtl util package.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
* Use new createTestDirectory. Fixes #452.
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* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing
* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
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* [stevo]: add reset initialization to shift register
* [stevo]: better comment
* [stevo]: add tests, fix bug
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Resolves #357
Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl
programmatically is preferred to on the command line. Update README to
indicate that Firrtl need not be installed.
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Fixing a bug in passing down execution options to firrtl
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* Name propagation
* chiselName everywhere at best-effort level
* Better collision handling
* Allow recursing into inner anonymous functions
* Add for loop and anonymous inner function tests
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Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.
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* Mark Annotation and FixedPoint as experimental
Fix tests and other references to these constructs
* Made experimental imports more specific where possible
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Pass transforms along with Annotations when calling firrtl compiler
This introduces new requirement that firrtl.Transform subclasses (that are associated with an annotation) do not have parameters in their default constructor
Add new test for NoDedup annotation that shows how to annotate a module instance
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* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use
* Somehow missed ChiselAnnotation
* fixes for Jack's review of PR
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Add examples for utils, move examples from individual apply methods to class overview scaladoc
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(#387)
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Get rid of some cruft exposed in #373
This also allows Bits.fromtInt(...) to be removed. Yay!
All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.
The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.
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Remove modName from Module
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compatibility package object
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
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Also, remove no-longer-special case for n=1.
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* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
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Add a cloneType method to QueueIO
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This causes Verilator tests to compile faster and use less memory
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