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path: root/src/main/scala/chisel3
AgeCommit message (Expand)Author
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-15Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280)Wesley W. Terpstra
2016-09-13Bugfix: actually pass flow parameter from Queue factory to Queue module const...Henry Cook
2016-09-08Add IrrevocableIO alternative to DecoupledIO (#274)Henry Cook
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-08-25fix a bug in setModNameDonggyu Kim
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-08-09counter(inc,n) example should reflect actual use (#252)Colin Schmidt
2016-07-31Remove deprecated FileSystemUtilitiesAndrew Waterman
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-11bitpat should keep the width of uint (#232)Donggyu
2016-07-07Improve QoR for Log2Andrew Waterman
2016-07-07Improve Fill code generationAndrew Waterman
2016-07-07Correct erroneous Log2 documentationAndrew Waterman
2016-07-07Avoid needlessly creating VecsAndrew Waterman
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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