summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3/verilog.scala
AgeCommit message (Expand)Author
2024-06-04Add partial util files so that it successfully compilesAditya Naik
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
2022-01-10Apply scalafmtJack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl