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#2935) (#2936)
* TruthTable improvements: structural equality and delete sort (#2935)
We had implemented equals, but not hashCode. This commit also changes
the implemental of equals to just use the underlying values instead of
wasting the compute calling .toString.
Delete TruthTable.sort, it is unused.
(cherry picked from commit b5d9c08b2d0994b94df2380425282206fe1f25bc)
* Restore and deprecate TruthTable.sort
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Fix BitSet decoder API when errorBit=False
When errorBit is set to False, the original code will return
`Unit` which will be `()` in interpolated string.
* Add testcases for both errorBit cases in BitSetSpec
(cherry picked from commit 42416cb6c6a3019fc29b9d98cfea3e3bb4e42684)
Co-authored-by: Ocean Shen <30361859+OceanS2000@users.noreply.github.com>
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#2612) (#2620)
* Refactor TruthTable.apply and add factory method for Espresso (#2612)
Improves performance of creating TruthTables by processing entire BitPats
rather than individual bits. New TruthTable factory method enables
constructing TruthTables with semantics of OR-ing output BitPats together
rather than erroring when multiple terms have the same input BitPat.
This alternative factory method matches semantics for the output format
of Espresso.
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 231f14e74f112a9f721e774561126b2bd1250039)
# Conflicts:
# src/main/scala/chisel3/util/BitPat.scala
* Resolve backport conflicts
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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Widths are now padded to the maximum width of the inputs.
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38)
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
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* Fix the QMC bug for constant and dontcare output.
* Fix the Espresso bug for constant and dontcare output.
(cherry picked from commit 46b53320e9ec09fc26d63259f1821f4234640839)
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
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Command:
sbt scalafmtAll
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BitSet is a new experimental parent type for BitPat.
It enables more complex operations on BitPats.
Co-authored-by: Ocean Shen <shenao6626@gmail.com>
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This makes the resulting Verilog from decoding a TruthTable deterministic.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add Y and N to BitPat.
* add ## for BitPat.
* add rawString API.
* use rawString in decoder
* add select and slice to BitPat.
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Co-authored-by: Haoran Yuan <sinofp@tuta.io>
Co-authored-by: Boyang Han <yqszxx@gmail.com>
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1. `TruthTable` is final now.
2. add return type for `TruthTable`
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This annotation adds memory import with inline generation for the
emmiter.
Supports both readmemh and readmemb statements based on argument.
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If a method passed to higher function does not return any value,
it is prefer to use `foreach` instead of `map`.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Added forcename transform and tests
* Added documentation and additional error checking
* Added mdoc. Added RunFirrtlTransform trait
* Removed TODO comment
* Addressed reviewer feedback
* Removed trailing comma
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* fix loadMemoryFromFile to work with binary
Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation
* Added test for binary format support in loadMemoryFromFile
* Added test for binary format support in loadMemoryFromFile
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* Added group chisel API
* Removed println
* Added scaladoc
* Added more tests
* Cleaned spacing and removed println
Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This fixes a bug where internal boring using BoringUtils.bore would
fail because it was using instanceName which cannot be called before
the module closes. Previously, this meant that BoringUtils.bore would
work for boring instances (which are closed in a parent), but not for
boring signals in the current, unclosed module.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This moves the documentation for loadMemoryFromFile onto the object as
opposed to the apply method. This includes additional cleanup in terms
of fixing uses of "$", topical grammar/capitalization, and adding more
outbound links.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This compresses the Scaladoc for BoringUtils slightly by using 120
character lines and removing unnecessary whitespace.
This also changes the poorly named "dedup" parameter to the what it
actually is: "disableDedup".
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This fixes a bug where BoringUtils non-hierarchical sinks would be
deduplicated even when specified that they should not be.
h/t @ucbjrl for discovering this!
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Quickfix for LoadMemoryTransform that gets this to work with Instance
Annotations. The new Instance Annotations caused a corner case where a
LoadMemoryAnnotation would be duplicated (via update/renaming) and the
resulting annotation would differ from the original in only their
originalMemoryNameOpt field. This corrects that by having the
ChiselLoadMemoryAnnotation also emit the originalMemoryNameOpt field where
it did not previously.
First part of a fix for freechipsproject/firrtl#922.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Ability to load memories at simulation startup
* first pass
* create annotation
* create skeleton Transform
* Work in progress
Building out transform and pass now
* Support for LoadMemory annotation
* Creates chisel and firrtl LoadMemory annotations
* LoadMemoryTransform converts annotation into BlackBox InLine
* Simple test that verilog bound modules get created.
* Support for LoadMemory annotation
* Supports Bundled/multi-field memories
* more tests
* support for `$readmemh` and `$readmemb`
* warns if suffix used in file specification.
* Support for LoadMemory annotation
* Use standard chisel annotation idiom
* Support for LoadMemory annotation
* Fixes for @seldridge nits and super-nits
* Support for LoadMemory annotation
- transform now only runs if emitter is an instance of VerilogEmitter
- suffixes on memory text files are now respected
- if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix
- every bind module created gets a unique number
- this is required when multiple loaded memories appear in a module
- this should be generalized for other uses of binding modules
* Support for LoadMemory annotation
- remove un-needed suffix test
* Support for LoadMemory annotation
- remove instance walk, now just processes each module
* Support for LoadMemory annotation
- Move LoadMemoryTransformation into Firrtl for treadle to access it.
* Support for LoadMemory annotation
- One more bug in suffix handling has been eliminated
* Support for LoadMemory annotation
- remove unused findModule per jackkoenig
- fixed complex test, bad filename edge case
* Support for LoadMemory annotation
- changed to not use intellij style column alignment for : declarations
* Load memory from file
Fixes based on @jkoenig review
- remove unused BindPrefixFactory
- Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom
- Made map to find relevant memory annotations faster
- Made map to find modules referenced by annotations faster
- Made things private that should be private
- DefAnnotatedMemorys are no longer referenced, shouldn't be found here.
- println of error changed to failed
* Loading memories from files
- Many changes based on review
- move stuff into experimental
- clean up annotation manipulation
- manage tests better
- use more standard practices for transform
* Loading memories from files
- More review changes
- Move doc from annotation to the object apply method that generates the annotation
- Make scalastyle directives more specific
- Use more efficient collect to generate name to module map
- Made lines obey style length limit
- a couple of cleanups of imports in tests
- removed some commented out code
- optimized checking for lines using .exists
- use _ for unused variable in match
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This adds a new trait, FlattenInstance, to chisel3.util.experimental. When
mixed into a module or a specific instance this trait will "flatten",
i.e., "inline that module and all of its submodules".
This includes testing (additions to InlineSpec) and ScalaDoc
documentation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds a new trait, InlineInstance, to chisel3.util.experimental. This
trait, when mixed into a specific module or instance, will "inline" that
module, i.e., "collapse a module while preserving it's submodules."
This includes testing (InlineSpec) and ScalaDoc documentation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an annotator that provides a linkage to the FIRRTL
WiringTransform. This enables synthesizable cross module references
between one source and multiple sinks without changing IO (the
WiringTransform bores through the hierarchy).
Per WiringTransform, this will connect sources to their closest
sinks (as determined by BFS) or fail if ownership is indeterminate.
Make TesterDriver.execute work like Driver.execute:
- annotations are included when running FIRRTL
- custom transforms are run automatically
Also, add a bore method to BoringUtils that allows you to do one source to
multi-sink mapping in a single call. This adds a test that this is doing
the same thing as the equivalent call via disjoint addSink/addSource.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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