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path: root/src/main/scala/chisel3/util/experimental
AgeCommit message (Expand)Author
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2018-10-29Fix LoadMemoryTransform for Instance Annotations (#914)Schuyler Eldridge
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
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