summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3/util/experimental
AgeCommit message (Expand)Author
2024-08-06Fix more misc fileschisel6-scala3-0.1Aditya Naik
2024-06-04Add partial util files so that it successfully compilesAditya Naik
2024-06-03fix stuff in src/Aditya Naik
2023-01-12TruthTable improvements: structural equality and delete sort (backport #2935)...mergify[bot]
2022-12-10Fix string interpolation in `util.exprimental.decode.bitset` (#2882) (#2883)mergify[bot]
2022-08-25Backport of eager error messages for annotations (3.5.x) (#2700) (#2705)Zachary Yedidia
2022-07-06Refactor TruthTable.apply and add factory method for Espresso (backport #2612...mergify[bot]
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
2022-01-10Apply scalafmtJack Koenig
2021-12-16BitSet API (#2211)Jiuyang Liu
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
2021-11-22add documentations to decoder. (#2254)Jiuyang Liu
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2018-10-29Fix LoadMemoryTransform for Instance Annotations (#914)Schuyler Eldridge
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 19:55:37 +0000