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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 2c2d72ceaa494b6acc351ff4300dbb40d4a7d863)
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Command:
sbt scalafmtAll
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* Change HasBlackBoxResource to Resolve Resources
Change HasBlackBoxResource to resolve resources immediately and emit
BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the
need for a FIRRTL compiler to grok the Java Resource API in order to
handle BlackBoxResourceAnno.
Emit BlackBoxInlineAnno from HasExtModuleResource instead of
BlackBoxResourceAnno.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* ExtModule's lacked support built in support for providing
the verilog source. This changes creates traits that
can be used with ExtModule to provide the support currently found in
BlackBox
- Add support for ExtModule helpers
- HasExtModuleResource to use addResource
- HasExtModuleInline to use setInline
- HasExtModulePath to use addPath
- Add tests of the above support.
- Note: These tests use Stage instead of Driver
- Added ScalaDoc for HasBlackBoxInline#setInline
* Fix the danged trailing commas.
* Change to use `.transform` as the correct API for `ChiselStage`
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* Add HasBlackBoxPath trait
* Use 'setResource' instead of 'addResource'
* Add ScalaDoc
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* Generalize ChiselAnnotation
This allows us to delay creation of Annotations till elaboration is
complete. Also update all annotation-related code.
* Add RunFirrtlTransform
Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old
ChiselAnnotation (now called ChiselLegacyAnnotation)
* Use unique test directories in ChiselRunners.compile
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* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing
* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
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