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path: root/src/main/scala/chisel3/Driver.scala
AgeCommit message (Expand)Author
2022-01-10Apply scalafmtJack Koenig
2021-11-29Deprecate chisel3.BackendCompilationUtilities (#2257)Jack Koenig
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Deprecate Driver Execution classesSchuyler Eldridge
2020-03-24Deprecate Driver methods in favor of ChiselStageSchuyler Eldridge
2020-02-19Migrate to Dependency WrapperSchuyler Eldridge
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
2019-08-27Move stack trimming from Driver to ChiselStageSchuyler Eldridge
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
2018-11-26Trim Stack Trace (#931)Albert Chen
2018-09-28Add dumpAnnotations method to DriverSchuyler Eldridge
2018-09-20Documentation tweaksedwardcwang
2018-07-02Direct to FIRRTL (#829)Jack Koenig
2018-02-28Refactor Annotations (#767)Jack Koenig
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-11-18Change Verilator invocation to use O1jackkoenig
2016-11-17Eliminate some doc warningsducky
2016-10-19Change verilogToCpp to use O0jackkoenig
2016-10-14Implement a standardized execution scheme for chiselchick
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-10-06Merge branch 'master' into buildinfoJim Lawson
2016-10-06Update Driver: Check the simulation exit code #281Jim Lawson
2016-10-05Print Chisel version when Driver object is created.Jim Lawson
2016-10-05Add sbt-buildinfo support.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Allow compileOptions as optional arguments to elaborate() and emit().Jim Lawson
2016-08-30Correct parameter name (topModule) in ScalaDoc.Jim Lawson
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