| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-05-05 | Move Chisel API into separate chiselFrontend compilation unit in preparation ... | ducky |
| 2016-05-04 | clock|reset to _clock|_reset, added explanatory comment | Stephen Twigg |
| 2016-05-04 | Rewrite BlackBox IO contract, replace _clock|_reset | Stephen Twigg |
| 2016-05-04 | Add HasId=Module|Data.suggestName, TransitName util | Stephen Twigg |
| 2016-04-14 | Eliminate RefMap | Andrew Waterman |
| 2016-01-28 | Use FIRRTL is invalid construct | Andrew Waterman |
| 2016-01-23 | Change implicit clock name to clk to match Chisel2 | Andrew Waterman |
| 2016-01-23 | Move firrtl subpackage to inside internal subpackage. | jackkoenig |
| 2015-12-11 | Add support for printf and asserts, add testbench for asserts and printf | ducky |
| 2015-12-06 | Split internal and FIRRTL packages | ducky |
| 2015-11-04 | Remove Parameters library and refactor Driver. | Henry Cook |
| 2015-10-26 | Break Core.scala into bite-sized pieces | ducky |
