summaryrefslogtreecommitdiff
path: root/src/main/scala/Chisel/Module.scala
AgeCommit message (Expand)Author
2016-05-05Move Chisel API into separate chiselFrontend compilation unit in preparation ...ducky
2016-05-04clock|reset to _clock|_reset, added explanatory commentStephen Twigg
2016-05-04Rewrite BlackBox IO contract, replace _clock|_resetStephen Twigg
2016-05-04Add HasId=Module|Data.suggestName, TransitName utilStephen Twigg
2016-04-14Eliminate RefMapAndrew Waterman
2016-01-28Use FIRRTL is invalid constructAndrew Waterman
2016-01-23Change implicit clock name to clk to match Chisel2Andrew Waterman
2016-01-23Move firrtl subpackage to inside internal subpackage.jackkoenig
2015-12-11Add support for printf and asserts, add testbench for asserts and printfducky
2015-12-06Split internal and FIRRTL packagesducky
2015-11-04Remove Parameters library and refactor Driver.Henry Cook
2015-10-26Break Core.scala into bite-sized piecesducky