summaryrefslogtreecommitdiff
path: root/src/main/scala/Chisel/Core.scala
AgeCommit message (Expand)Author
2015-08-11Remove useless call to getWidthAndrew Waterman
2015-08-10Fix Mux type safetyAndrew Waterman
2015-08-10Make Bits.toBool safeAndrew Waterman
2015-08-10Force toUInt = asUInt, toSInt = asSIntAndrew Waterman
2015-08-10Don't use cloneType for primopsAndrew Waterman
2015-08-10Remove redundant castAndrew Waterman
2015-08-10Allow SInt := SIntAndrew Waterman
2015-08-10Parameter cleanupHenry Cook
2015-08-09For now, allow constructing Data outside of ModulesAndrew Waterman
2015-08-09Regularize literal handlingAndrew Waterman
2015-08-08params must be public, as user modules refer to itAndrew Waterman
2015-08-08DRYAndrew Waterman
2015-08-06Merge branch 'driverRefactor'Henry Cook
2015-08-06dynamic scoping cleanupsHenry Cook
2015-08-06Terminate all conditional blocks with skipAndrew Waterman
2015-08-06Clean up after when-block refactoringAndrew Waterman
2015-08-06Simplify the implementation of when-blocksAndrew Waterman
2015-08-05cleanup Module factoryHenry Cook
2015-08-05make _mod less privateHenry Cook
2015-08-05refactor driver to use scoped DynamicVariables instead of static global stacksHenry Cook
2015-08-05Massive Driver simplification, some tweaks to Parameter apiHenry Cook
2015-08-05clean up Emitter a bitAndrew Waterman
2015-08-05Use Width object, not IntAndrew Waterman
2015-08-04Vecs are homogeneous, so implement them as suchAndrew Waterman
2015-08-04Clean up MuxAndrew Waterman
2015-08-04Reg(init=UInt(0,N)) should force Reg width to NAndrew Waterman
2015-08-04Refactor Bundle field enumerationAndrew Waterman
2015-08-04Add better cloneTypeWidth and deprecate old oneAndrew Waterman
2015-08-03Improve type-safety of switch/is blocks using macros and SwitchContext. Remov...Henry Cook
2015-08-03Fix << width bugAndrew Waterman
2015-08-03Don't zero-initialize for Wire(init=...)Andrew Waterman
2015-08-03No more shitballsAndrew Waterman
2015-08-02shitballsAndrew Waterman
2015-08-02Move comparison operators to UInt/SIntAndrew Waterman
2015-08-02soften permissions on dirVarHenry Cook
2015-08-02Work around FIRRTL initialization pedantryAndrew Waterman
2015-08-02Use flatMap instead of map/reduceAndrew Waterman
2015-08-01Compute node directions correctlyAndrew Waterman
2015-08-01When reflecting, sort fields for determinismAndrew Waterman
2015-08-01Clean up flip/asInput/asOutputAndrew Waterman
2015-07-31Disallow dynamic bit range extractionAndrew Waterman
2015-07-31Improve handling of := and <>Andrew Waterman
2015-07-31Implement getWidth more completely and less buggilyAndrew Waterman
2015-07-31Open heart surgery on IDs/namingAndrew Waterman
2015-07-30Work around FIRRTL literal restrictionsAndrew Waterman
2015-07-30Better literal checkingAndrew Waterman
2015-07-30Check for negative UInt literalsAndrew Waterman
2015-07-30Correct implementation of andRAndrew Waterman
2015-07-30Make Vec.fill(n)(x) the same as Vec(x, n)Andrew Waterman
2015-07-30Emit clocks and resetsAndrew Waterman
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 06:52:46 +0000