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(cherry picked from commit 68510515467ef7a86c54b2e710bfc5e736f7a2aa)
Co-authored-by: Gonsolo <gonsolo@gmail.com>
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(backport #2476) (#2479)
* Capture 1:1 mappings of Aggregates inside of views
This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).
This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.
(cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e)
* Add FlatIO API for creating ports from Bundles without a prefix
(cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb)
* [docs] Add FlatIO to the general cookbook
(cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit d4dd21191c63a3b125193a7ffb83d478aa945d5a)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Tweaks to the Verilog-vs-Chisel Page
* Update cookbook.md
* Update verilog-vs-chisel.md
* Update verilog-vs-chisel.md
(cherry picked from commit 7432bdff8369ba55db73c7934e41bb6f4060bb6d)
Co-authored-by: Megan Wachs <megan@sifive.com>
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(cherry picked from commit 98fdfc5e609099cb4fb1749132cc62236148c6da)
Co-authored-by: Megan Wachs <megan@sifive.com>
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Co-authored-by: Shola Ogunkelu @Shorla
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Deborah Soung <debs@sifive.com>
Completed as part of Outreachy Internship Dec 2021-March 2022.
(cherry picked from commit 362702f3fd79bf1071db4acecc679f25a0b94a8a)
Co-authored-by: Olushola Ogunkelu <77856859+Shorla@users.noreply.github.com>
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#naming implies within the current file. Removing the # refers to a file in the current directory.
(cherry picked from commit 512ddd6c8b079dd83f2a3ed793e6595822a382cb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* New Feature: Add a Select.ios that works with Definition/Instance
* BugFix: isA now truly ignores type parameters
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This new document is a place to describe issues users may run into when
upgrading from Chisel 3.4 to 3.5. This initial version includes the
solution for the removal of virtual method "val io".
Co-authored-by: Megan Wachs <megan@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* DataProducts for Seq and Tuple2-10 in DataProduct companion object
* DataViews for Seq and Tuple 2-10 in DataView companion object
* HWTuple2-10 Bundles in chisel3.experimental
* Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
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Remove the body from the emitted Verilog. This was the original intent
of the example, and it avoids an issue where Jekyll was not able to
render the Markdown file due to Verilog concatenation looking like a
variable escape.
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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Previously, the example had an extra wrapping module that led
to the interesting example getting optimized away.
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* Add Hierarchy trait
* Add Hierarchy trait
* Add Hierarchy scaladoc
* Add license
* Add isA and tests
* Add back isA
* Add new Select APIs for hierarchy package
* Update scaladoc
* Write outlines for tests
* Add tests and fixes to new Select functions
* Make calculate via lazy val
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Clean up scaladoc
* Add shouldNot compile
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Bugfix all funcs should analyze root too
* Add mdoc, bugfix toDefinition
* Make func private, add scaladoc
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Made protected vals private
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Address code review comments
* Added additional null check
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Update bundles-and-vecs.md
* Update docs/src/explanations/bundles-and-vecs.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update naming.md
Added a title to the cookbook
* Add name to Multiple Clock Domain page
* Update multi-clock.md
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Update docs README with instructions for new pages
* Update docs/README.md
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* Update bundles-and-vecs.md
* Update docs/src/explanations/bundles-and-vecs.md
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Update experimental-features.md
Added title to Experimental features
* Update experimental-features.md
* Update docs/src/appendix/experimental-features.md
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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Added cookbooks to cookbooks.md
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* Added dataview to explanations.md
* Update docs/src/explanations/explanations.md
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Added title
* Update docs/src/explanations/blackboxes.md
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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Added title to "Namimg Cookbook" website.
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Remove all manual cloneTypes and make it chisel runtime deprecated to add one
* runtime deprecate cloneType with runtime reflection
* [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later)
* Plugin: make it an error to override cloneType and add a test for that
* Docs: can't compile the cloneType anymore
* BundleSpec: comment out failing test I cannot get to fail or ignore
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Close #2138
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This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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* [docs] Add example of stripping directions from type
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Improve := comment
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.
A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.
If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.
DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.
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* Small changes to memory doc
- Fixed typo "except" => "accept"
- Use `Counter` explicitly in ROM section example.
* Fix counter doc compile error
* remove invisible doc block in memory example
* more small fixes to make mem example pass doc compile
* Get rid of sine wave iterator in memory doc
* get rid of tabs on VecInit example
* get rid of tabs on VecInit example
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* Add @ekiwi's code as a starting point
* Add test for ChiselEnum isOneOf method
* Make isOneOfTester naming consistent with other testers
* Add scaladoc comments for isOneOf
* Add isOneOf tests that use the method that takes variable number of args
* Add guide level documentation example for isOneOf
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Also add newline to end of `verilog` modifier code blocks so that there
is always a newline between code blocks and following material.
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* Add Clock
* Add Analog
* Add Interval
* Add line from User Types (...) to Record
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* Cookbook: clean up desiredName example
* Update cookbook.md
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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nitpick
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* Remove space between backticks and language
* Make code examples in memories explanation work
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add documentation guide about memory initialization
* Move information to experimental and add ref
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* Update the FAQ and add doc on versioning
* Update modules.md
Co-authored-by: Megan Wachs <megan@sifive.com>
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Updates to chisel3 documentation for website:
* guard code examples with mdoc and fix errors encountered along the way
* move some website content here vs splitting the content across two repos
* Bring in the interval-types and loading memories content so that it will be visible from the website
* remove all references to the wiki (deprecated)
* Remove reference to Wiki from the README
* fix tabbing and compile of chisel3-vs-chisel2 section
* Appendix: faqs now guarded and compile
* FAQs: move to resources section
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* Adding ChiselEnum Documentation Entry
Added documentation for the ChiselEnum type with verified examples
* Fixed some doc ambiguity and repeated emitVerilog calls
* Added ChiselStage and commented out package definition since packages cannot be declared in single files
* Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports
* Opps on not adding _ after import
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Modified Bundle for ci and made changes to select naming scheme
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Added missing backticks
* Added space around error block quote
* Fixed md paragraph in code
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
* Update docs/src/explanations/chisel-enum.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Fixed some comments and formatting
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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