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AgeCommit message (Expand)Author
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
2021-08-18Builder: downgrade "Elaborating design" message to info (#2081)Kevin Laeufer
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. (#1944)"...Jack Koenig
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
2021-08-12Add DataView (#1955)Jack Koenig
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
2021-07-14Fix Cat rename signal (#2011)Leway Colin
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
2021-07-08Update docs on dontTouch as optimization barrier (#2015)Schuyler Eldridge
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
2021-07-01Change Chisel warnings to use logger instead of printlnJack Koenig
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-29deprecate getPorts with modulePorts. (#1945)Jiuyang Liu
2021-06-28Set refs for ModuleClone and ClonePorts in less hacky wayJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-25Correct typos in core/src/main/scala/chisel3/Num.scala (#1976)Felix Yan
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
2021-04-26Add some error context to Converter .getRefs (#1878)Jack Koenig
2021-03-29Provide useful message on Vec.apply require (#1838)Jack Koenig
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12[plugin] Stop autoclonetype stack traces when using pluginJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-24Aggregate: fix typo (#1789)edwardcwang
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
2021-02-09Make it possible to GC Data instancesJack Koenig
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
2021-01-27Fix incorrect comment in ScalaDoc (#1756)Jack Koenig
2021-01-24Refactor EnumAnnotations and EnumFactory (#1747)SoyaOhnishi
2021-01-21Apply suggestions from code reviewJack Koenig
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
2021-01-21Deprecate override_clock and override_reset in ModuleJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2021-01-20remove 2.11 dedicated code. (#1744)Jiuyang Liu
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not serialize...Megan Wachs
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message (#...Jiuyang Liu
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
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