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* Define leading '_' as API for creating temporaries
Chisel and FIRRTL have long used signals with names beginning with an
underscore as an API to specify that the name does not really matter.
Tools like Verilator follow a similar convention and exclude signals
with underscore names from waveform dumps by default. With the
introduction of compiler-plugin prefixing in Chisel 3.4, the convention
remained but was hard for users to use unless the unnnamed signal
existed outside of any prefix domain. Notably, unnamed signals are most
useful when creating wires inside of utility methods which almost always
results in the signal ending up with a prefix.
With this commit, Chisel explicitly recognizes signals whos val names
start with an underscore and preserve that underscore regardless of any
prefixing. Chisel will also ignore such underscores when generating
prefixes based on the temporary signal, preventing accidental double
underscores in the names of signals that are prefixed by the temporary.
(cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6)
* Remove unused defaultPrefix argument from _computeName
(cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554)
# Conflicts:
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
* Resolve backport conflicts
* Waive false positive binary compatibility errors
Co-authored-by: Jack Koenig <koenig@sifive.com>
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option (#2575) (#2579)
* Added ImplicitInvalidate trait with tests
(cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
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(cherry picked from commit 255c56c3955a8c16191a6751e7d547cfcfd96705)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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* Factor buildName into reusable function
The new function is chisel3.internal.buildName.
(cherry picked from commit 370ca8ac68f6d888dd99e1b9e63f0371add398cf)
* Add --warn:reflective-naming
This new argument (and associated annotation) will turn on a warning
whenever reflective naming changes the name of a signal. This is
provided to help migrate from Chisel 3.5 to 3.6 since reflective naming
is removed in Chisel 3.6.
(cherry picked from commit 97afd9b9a1155fa7cd5cedf19f9e0c15fbe899ec)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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#2534) (#2559)
* Deprecate .U() and .S() syntax for literal bit extracts (#2534)
(cherry picked from commit cadaf33a650ef898fdab2f81244e4ad6a07a9ea8)
# Conflicts:
# macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
* Fix backport conflict (#2560)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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This is a formatted version of the p"..." interpolator analogous to
Scala's f"..." interpolator. The primary difference is that it supports
formatting interpolated variables by following the variable with
"%<specifier>". For example:
printf(cf"myWire = $myWire%x\n")
This will format the hardware value "myWire" as a hexidecimal value in
the emitted Verilog. Note that literal "%" must be escaped as "%%".
Scala types and format specifiers are supported and are handled in the
same manner as in standard Scala f"..." interpolators.
(cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b)
Co-authored-by: Girish Pai <girish.pai@sifive.com>
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This includes (and is tested) for both the old .*Name APIs and
.toTarget
(cherry picked from commit 6e0d8d6b12e9d8f94c2cc43b92b2366ec70dfd50)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.
(cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(backport #2512) (#2520)
* Support separately elaborating definition and instance in ChiselStage (#2512)
(cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8)
# Conflicts:
# core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala
# core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala
# core/src/main/scala/chisel3/internal/Builder.scala
* fixing imports (#2522)
Co-authored-by: Deborah Soung <debs@sifive.com>
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(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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The difference in logic depth for various paths now has a maximum of 1.
Also make treeReduce order the same for 2.12 and 2.13
.grouped(_) returns an Iterator
.toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13
This can lead to changes in order when bumping from 2.12 to 2.13 that
can be avoided by simply using an eager collection explicitly.
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c)
Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
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Fixes #2470
(cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a)
Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
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This is a quick fix for issue #2408
(cherry picked from commit d4ef9a96c4131252a0a49002a28be3391eb67258)
Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
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(cherry picked from commit 52165fe2796d08c664069c148868aedc64ea3777)
Co-authored-by: Lucheng Zhang <79909456+geekLucian@users.noreply.github.com>
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(cherry picked from commit d6a357d29cfa7120b3c0c90684b33be1863e5599)
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa)
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Use a single field instead of two in HasId (4-bytes per HasId)
* Set the prefix to Nil after setting ref to free up memory
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 3aa179f0dc1a29403fd25be7d3dc08630976d018)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(backport #2476) (#2479)
* Capture 1:1 mappings of Aggregates inside of views
This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).
This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.
(cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e)
* Add FlatIO API for creating ports from Bundles without a prefix
(cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb)
* [docs] Add FlatIO to the general cookbook
(cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* During sanitize, only filter the String if needed
* Do not recurse on name, saving an unnecessary call to sanitize
(cherry picked from commit 559b3df3e5bd6c73588638aa44a6df1244a11a53)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 3940136bec72fc44e40d454f2c2dcc421fc92d82)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f)
Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>
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This reduces memory use of every HasId by 64 bytes.
Every instance of HasId (including all Data) had 2 ListBuffer vals for
recording post-naming hooks, yet this feature is almost never used.
These are now vars of type List which allows the common case of Nil to
add no incremental memory use per instance of HasId.
(cherry picked from commit cf410180ac8de854d8d7ecf89f4813ac8541dcdb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.
Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Also delete an errant println in InstanceSpec
(cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Issue errors on out-of-range extracts when width is known
Firrtl will catch this later on, but better to error early if possible.
* Test that errors are generated on OOB extracts when width is known
(cherry picked from commit 462def429aa87becb544533880a3075a806c53e4)
Co-authored-by: Andrew Waterman <andrew@sifive.com>
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(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989)
Co-authored-by: Deborah Soung <debs@sifive.com>
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(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730)
Co-authored-by: Megan Wachs <megan@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 015755749caa8a05f3809d446b023df80c7419d1)
Co-authored-by: Tynan McAuley <tynan@galois.com>
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* Only call _elementsImpl once in Bundle.elements
* Distinguish compiler plugin and reflective _elementsImpl
Bundle.elements now will only do post-processing if the user is using
plugin-generated _elementsImpl. This improves performance for the case
where the user does not opt-in to using the plugin to generate
_elementsImpl.
(cherry picked from commit 5fead89ee0132355e551bcb6b87cc2a6db679bee)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Change type of Bundle._elementsImpl to Iterable
It was previously SeqMap (ListMap on Scala 2.12). This change gives us
more freedom to optimize the implementation without breaking binary
compatibility. It is scala.collection.Iterable because it is perfectly
fine to return mutable collections (like Arrays) since the only use is
to Iterate on them.
* Disallow users implementing Bundle._elementsImpl
Currently, it would result in a runtime linkage error. This turns it
into a compile-time error.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 1b05a14ad6d5784f3b91ab510dc1095423c23ea8)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Use Builder.deprecated instead of Builder.warning so that the warnings
are aggregated by source locator to prevent spamming the screen with
duplicated warnings.
(cherry picked from commit 538e223ae81c8b66a4123303f6dab61c874aaa1e)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Improve error reporting (#2376)
* Do not trim stack traces of exceptions with no stack trace
This prevents us from accidentally giving stack traces to exceptions
that don't have them and giving misleading messages telling users to use
--full-stacktrace when it won't actually do anything.
Also deprecate ChiselException.chiselStackTrace which is no longer being
used anywhere in this codebase.
* Add exception class for multiple-errors reported
New chisel3.internal.Errors replaces old anonymous class that would show
up as chisel3.internal.ErrorLog$$anon$1 in error messages.
* Add new option --throw-on-first-error
This tells Chisel not to aggregate recoverable errors but instead to
throw an exception on the first one. This gives a stack trace for users
who need it for debugging.
(cherry picked from commit ff2e9c92247b3848659fa09fdd53ddde2120036a)
* Waive MiMa false positives
The waived change is to a package private constructor.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Warn if clock at memory instantiation differs from clock bound at port
creation and port clock is not manually passed
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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Adds generation of `Bundle.elements` method to the chores done by the compiler plugin
For each `Bundle` find the relevant visible Chisel field members and construct a
hard-coded list of the elements and their names implemented as `_elementsImpl`
For more details: See plugins/README.md
- Should be no change in API
- Handles inheritance and mixins
- Handles Seq[Data]
- Tests in BundleElementSpec
Co-authored-by: chick <chick.markley@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 237200a420581519f29149cbae9b3e968c0d01fc)
Co-authored-by: Chick Markley <chick@qrhino.com>
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The new reflection based IO autowrapping for compatibility mode Modules
would previously throw a NullPointerExceptions if any hardware were
constructed in the Module before "val io" was initialized. The logic is
now more robust for this case.
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 50e6099fbecc041973564514e55f67ffe069459b)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add Lookupable for Either
* Lookupable: enhance the @public/@instantiable error message to include traits and Eithers
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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* New Feature: Add a Select.ios that works with Definition/Instance
* BugFix: isA now truly ignores type parameters
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This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a.
Note that I am keeping the change making Arg sealed.
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- Shows groups of field names that share a common id (i.e. aliased)
- Show, as much as possible, them in the order that fields appear in bundle
- Updated BundleSpec's relevant tests
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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preserves input/output information of the type being reduced.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
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* DataProducts for Seq and Tuple2-10 in DataProduct companion object
* DataViews for Seq and Tuple 2-10 in DataView companion object
* HWTuple2-10 Bundles in chisel3.experimental
* Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
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