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authormergify[bot]2022-06-13 19:11:33 +0000
committerGitHub2022-06-13 19:11:33 +0000
commit13641d95951b189d7f5b0d4d99ace45f8b8f6282 (patch)
tree863345c541b7edac7b04b717e0690506c120ea14 /core/src/main/scala/chisel3
parent4b8981d627fc307161ff39b78836e37212803756 (diff)
Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler option (#2575) (#2579)
* Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3')
-rw-r--r--core/src/main/scala/chisel3/Data.scala2
-rw-r--r--core/src/main/scala/chisel3/Module.scala2
-rw-r--r--core/src/main/scala/chisel3/RawModule.scala7
3 files changed, 7 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index f468335e..77ad66ef 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -866,7 +866,7 @@ trait WireFactory {
x.bind(WireBinding(Builder.forcedUserModule, Builder.currentWhen))
pushCommand(DefWire(sourceInfo, x))
- if (!compileOptions.explicitInvalidate) {
+ if (!compileOptions.explicitInvalidate || Builder.currentModule.get.isInstanceOf[ImplicitInvalidate]) {
pushCommand(DefInvalid(sourceInfo, x.ref))
}
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 08286ed5..d03122f9 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -386,7 +386,7 @@ package internal {
clonePorts.setAllParents(Some(cloneParent))
cloneParent._portsRecord = clonePorts
// Normally handled during Module construction but ClonePorts really lives in its parent's parent
- if (!compileOptions.explicitInvalidate) {
+ if (!compileOptions.explicitInvalidate || Builder.currentModule.get.isInstanceOf[ImplicitInvalidate]) {
// FIXME This almost certainly doesn't work since clonePorts is not a real thing...
pushCommand(DefInvalid(sourceInfo, clonePorts.ref))
}
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 164d3880..bd04fdc4 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -147,7 +147,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
// Generate IO invalidation commands to initialize outputs as unused,
// unless the client wants explicit control over their generation.
val invalidateCommands = {
- if (!compileOptions.explicitInvalidate) {
+ if (!compileOptions.explicitInvalidate || this.isInstanceOf[ImplicitInvalidate]) {
getModulePorts.map { port => DefInvalid(UnlocatableSourceInfo, port.ref) }
} else {
Seq()
@@ -161,7 +161,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
implicit val sourceInfo = UnlocatableSourceInfo
- if (!parentCompileOptions.explicitInvalidate) {
+ if (!parentCompileOptions.explicitInvalidate || Builder.currentModule.get.isInstanceOf[ImplicitInvalidate]) {
for (port <- getModulePorts) {
pushCommand(DefInvalid(sourceInfo, port.ref))
}
@@ -177,6 +177,9 @@ trait RequireSyncReset extends Module {
override private[chisel3] def mkReset: Bool = Bool()
}
+/** Mix with a [[RawModule]] to automatically connect DontCare to the module's ports, wires, and children instance IOs. */
+trait ImplicitInvalidate { self: RawModule => }
+
package object internal {
import scala.annotation.implicitNotFound