| Age | Commit message (Collapse) | Author |
|---|
|
(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
|
|
This is a formatted version of the p"..." interpolator analogous to
Scala's f"..." interpolator. The primary difference is that it supports
formatting interpolated variables by following the variable with
"%<specifier>". For example:
printf(cf"myWire = $myWire%x\n")
This will format the hardware value "myWire" as a hexidecimal value in
the emitted Verilog. Note that literal "%" must be escaped as "%%".
Scala types and format specifiers are supported and are handled in the
same manner as in standard Scala f"..." interpolators.
(cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b)
Co-authored-by: Girish Pai <girish.pai@sifive.com>
|
|
(cherry picked from commit d6a357d29cfa7120b3c0c90684b33be1863e5599)
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
|
|
Command:
sbt scalafmtAll
|
|
Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
|
|
|
|
* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
|
