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path: root/core/src/main/scala/chisel3/Mem.scala
AgeCommit message (Expand)Author
2024-06-03Get core to compileAditya Naik
2024-05-31Remove sourceinfo, compileoptions and other fixesAditya Naik
2024-05-3152 errors, removing implicit sourceinfo to clear more errorsAditya Naik
2024-05-29i got 99 errors but "firrtl not found" aint oneAditya Naik
2022-09-01Remove incorrect clock warning on Mem.read (backport #2721) (#2722)mergify[bot]
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
2022-01-10Apply scalafmtJack Koenig
2021-10-05Deprecate auto-application of empty argument lists to parameterless functions...Jared Barocsi
2021-08-30SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)Kevin Laeufer
2021-02-09Make it possible to GC Data instancesJack Koenig
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-07-31Check whether signals escape their when scopes (#1518)Albert Magyar
2020-03-25Rename subprojects to more canonical namesJack Koenig
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