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2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09Legalize identifier names before printingAndrew Waterman
It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being.
2016-08-04Deal with directions on Clocks.Jim Lawson
2016-08-03Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-31Expose asUInt from DataAndrew Waterman
Deprecating toBits removes the capability to cast an arbitrary type to UInt. While it's still possible to do so using asBits.asUInt, this creates boilerplate. (asBits is almost never useful itself.)
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-28Add missing factory constructors.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_].
2016-07-20Compile ok.Jim Lawson
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Remove explicit literal binding.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
Compiles but fails tests.
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-07-15Improve PopCount implementationAndrew Waterman
Clean up Scala code, and use +& to generate a lot less FIRRTL
2016-07-01Reflectively name Module fields declared in superclassesAndrew Waterman
Closes #229 h/t @sdtwigg @davidbiancolin
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-23Expose FIRRTL stop constructAndrew Waterman
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-20fix BlackBox setRefs to correctly handle arbitrarily nested bundles as ports ↵Howard Mao
(#223)
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
2016-06-15Generate better node names when names collide (#221)Andrew Waterman
Rather than using a global counter, memoize the last returned value for colliding names to generate smaller sequence numbers.
2016-06-08Move deprecated debug into compatibilityducky
2016-06-08Package split chisel coreducky
2016-06-08Move chisel/... to chisel/core/..., make chisel/compatibility ↵ducky
package/folder, move more things into utils
2016-06-08Rename packages to lowercase chisel, add compatibility layerducky
2016-06-08For Module instances we haven't named, suggest the Module class nameAndrew Waterman
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
* chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR.
2016-05-31Move BitPat out of core/frontend, add implicit conversionDucky
2016-05-26Fix type constraint on PriorityMuxAndrew Waterman
2016-05-20Merge pull request #186 from ucb-bar/sloc_implRichard Lin
Source locators
2016-05-20Implementation of source locatorsducky
2016-05-10Some -> OptionDonggyu Kim
Option(null) returns None, but Some(null) returns Some(null)
2016-05-10Move emit out of IRducky
2016-05-10Have Bits.toBools return Seq, not VecAndrew Waterman
The return value of Bits.toBools doesn't need to be dynamically indexed (as you could have just dynamically indexed the Bits itself), so returning a Seq instead of a Vec is mroe appropriate. This breaks a circular dependence between Bits and Vec, which helps with macros/frontend refactoring.
2016-05-10Relax Mem write-masks to Seq, rather than VecAndrew Waterman