| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-07-28 | Add missing factory constructors. | Jim Lawson | |
| 2016-07-27 | Additional compatibility code. | Jim Lawson | |
| 2016-07-25 | Enable current (chisel2-style) compatibility mode. | Jim Lawson | |
| 2016-07-25 | Minimize differences with master. | Jim Lawson | |
| Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. | |||
| 2016-07-25 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-21 | Introduce chiselCloneType to distinguish from cloneType. | Jim Lawson | |
| Still fails one test - DirectionSpec in Direction.scala | |||
| 2016-07-20 | More literal/width rangling. | Jim Lawson | |
| 2016-07-20 | Distinguish between ?Int.Lit and ?Int.width | Jim Lawson | |
| 2016-07-20 | Generate better names for nodes (#190) | Jack Koenig | |
| For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_]. | |||
| 2016-07-20 | Compile ok. | Jim Lawson | |
| Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x) | |||
| 2016-07-19 | Fixes for only connectwrap version. | Jim Lawson | |
| 2016-07-19 | Merge in "complete" versions of Mem, Reg. | Jim Lawson | |
| 2016-07-19 | Fix LitBinding and MultiAssign tests. | Jim Lawson | |
| 2016-07-19 | Remove explicit literal binding. | Jim Lawson | |
| 2016-07-19 | Incorporate connection logic. | Jim Lawson | |
| Compiles but fails tests. | |||
| 2016-07-19 | Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3 | Jim Lawson | |
| 2016-07-18 | Update Chisel -> chisel3 references. | Jim Lawson | |
| 2016-07-18 | Rename "Chisel" to "chisel3" (only git mv). | Jim Lawson | |
| 2016-07-15 | Improve PopCount implementation | Andrew Waterman | |
| Clean up Scala code, and use +& to generate a lot less FIRRTL | |||
| 2016-07-01 | Reflectively name Module fields declared in superclasses | Andrew Waterman | |
| Closes #229 h/t @sdtwigg @davidbiancolin | |||
| 2016-06-24 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-22 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-20 | Rename "package", "import", and explicit references to "chisel3". | Jim Lawson | |
| 2016-06-20 | Rename chisel3 package. | Jim Lawson | |
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index : chiselX | |
| Chisel with SFC compatibility |
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