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path: root/chiselFrontend/src/main/scala/chisel3/internal
AgeCommit message (Collapse)Author
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
In the Chisel frontend, the implicit clock is named clock, but in the generated FIRRTL, it is named clk. There is no reason for this discrepancy, and yet fixing it is painful, as it will break test harnesses. Better to take the pain now than later. Resolves #258.
2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-08-24Per Chisel meeting.chick
signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-09Legalize identifier names before printingAndrew Waterman
It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being.
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson