summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
AgeCommit message (Expand)Author
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-12Use compileOptions to determine if Missing...FieldExceptions are thrown.Jim Lawson
2016-08-12Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-12Add support for per-Module compilation options.Jim Lawson
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Legalize identifier names before printingAndrew Waterman
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson