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2021-03-18Update the FAQ and add doc on versioning (#1827)Jack Koenig
* Update the FAQ and add doc on versioning * Update modules.md Co-authored-by: Megan Wachs <megan@sifive.com>
2021-03-18Reorganize website docs (#1806)Megan Wachs
Updates to chisel3 documentation for website: * guard code examples with mdoc and fix errors encountered along the way * move some website content here vs splitting the content across two repos * Bring in the interval-types and loading memories content so that it will be visible from the website * remove all references to the wiki (deprecated) * Remove reference to Wiki from the README * fix tabbing and compile of chisel3-vs-chisel2 section * Appendix: faqs now guarded and compile * FAQs: move to resources section
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12Merge pull request #1804 from chipsalliance/autoclonetype2Jack Koenig
Compiler plugin implemented autoclonetype
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Stop autoclonetype stack traces when using pluginJack Koenig
The compiler plugin obviates the need for using stack traces to determine outer objects in autoclonetype. When the plugin was used to compile a given Bundle, it will no longer collect a stack trace upon construction. This should have massive benefits to elaboration runtime.
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11[plugin] Split ChiselComponent into its own fileJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument.
2021-03-03Add header for chisel-enum.md (#1800)Jack Koenig
2021-03-02Adding ChiselEnum Documentation Entry (#1795)chrisbaldwin2
* Adding ChiselEnum Documentation Entry Added documentation for the ChiselEnum type with verified examples * Fixed some doc ambiguity and repeated emitVerilog calls * Added ChiselStage and commented out package definition since packages cannot be declared in single files * Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports * Opps on not adding _ after import * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Modified Bundle for ci and made changes to select naming scheme * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Added missing backticks * Added space around error block quote * Fixed md paragraph in code * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Fixed some comments and formatting Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-24Aggregate: fix typo (#1789)edwardcwang
Not a Pokémon
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
* Handle MemTypeBinding in Analog Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-02-10Merge pull request #1624 from chipsalliance/gc-dataJack Koenig
Make Data GC-able
2021-02-09Make it possible to GC Data instancesJack Koenig
No longer create a pointer from parent to every HasId, only do it by default for BaseModules and MemBases. Add pointer from parent to Data upon binding the Data. * Add MemTypeBinding for port types of Mems This binding is similar to the SampleElementBinding for Vecs in that these Data are not truly hardware, but are represented in the FIRRTL IR and thus need some representation. * Call _onModuleClose on unbound Records This maintains some corner-case behavior that is nevertheless relied upon. It ensures that refs are set for the elements of Records, even if they are not bound to any real hardware.
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
This is a new SBT build unit that symlinks in some files from the normal chisel project tests, but builds them without the compiler plugin.
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
* Added SyncReadMem-based implementation of the Queue class * Rework of the parametrized Queue class SyncReadMem-based implementation * Modification of the parametrized Queue class SyncReadMem-based implementation * Limiting the visibility of the read address for SyncReadMem-based Queue Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-05Add file line to source link from scaladoc (#1776)John's Brew
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
2021-02-04Minor docs improvements (#1774)Jack Koenig
* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc) * Replace some unnecessary uses of triple backticks with single backticks * Move appendix docs from wiki-deprecated/ to appendix/ * This will require an update on the website as well * Update Bundle literal docs
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-02-01Bump to Scala 2.12.13 (#1766)Jack Koenig
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-27Fix incorrect comment in ScalaDoc (#1756)Jack Koenig
2021-01-24Refactor EnumAnnotations and EnumFactory (#1747)SoyaOhnishi
This is a nit fix. no logic is changed. * Rename `typeName` to `enumTypeName` in ScalaDoc * Add return type at public method * Rename `enum_records` into `enumRecords` to retain name consistency Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-01-22Add redirect for Scala 2.11 upgrade page (#1749)Jack Koenig
2021-01-21Merge pull request #1745 from chipsalliance/remove-val-ioJack Koenig
Remove "val io" and rename MultiIOModule to Module
2021-01-21Apply suggestions from code reviewJack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com>
2021-01-21Update docs for the removal of val io and MultiIOModuleJack Koenig
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
2021-01-21Deprecate override_clock and override_reset in ModuleJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2021-01-20remove 2.11 dedicated code. (#1744)Jiuyang Liu
This PR revert #1480, but keep the test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-20Fix Mergify condition for labeling backports (#1742)Jack Koenig
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
This is useful for libraries to guard operations implemented via annotations or BlackBoxes by the current when predicate
2021-01-15Merge pull request #1732 from chipsalliance/farewell_scala_211Jack Koenig
Farewell Scala 2.11
2021-01-15farewell Scala 2.11Jiuyang liu
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not ↵Megan Wachs
serialize properly) (#1714) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget
2021-01-06Update meeting url (#1716)Jiuyang Liu
2020-12-17Automate publishing of SNAPSHOTS with sbt-ci-release (#1706)Jack Koenig
2020-12-17Remove CircleCI (#1702)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-17Bump SNAPSHOT and SNAPSHOT dependencies (#1701)Jack Koenig
2020-12-16Switch to using Github Actions CI (#1690)Jack Koenig
MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x
2020-12-08Make Maven show chisel3 as apache-2.0 (#1695)Chick Markley
- fix build.sbt - fix build.sc
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