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* spot a bug when BitPat width is 0
* fix #1919
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* implement pla
* implement test for pla
* implement inverter matrix of PLA generator
* fix for review.
Co-authored-by: Boyang Han <yqszxx@gmail.com>
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* add os-lib to dependency.
* implement EndToEndSMTBaseSpec
* rename to SMTModelCheckingSpec
* add documentation.
* fix for review.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update scalacheck-1-14, ... to 3.1.4.0
* Update scalacheck-1-14, ... to 3.1.4.0
* Update scalacheck-1-14 to 3.1.4.0
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add test to check ShiftRegister(s) with delay is 0.
This should break ShiftRegister(x, 0) since last is not exist in a empty
Seq. Originally, test only test 1 to 4, which missed a potential bug
from #1723.
* Fix ShiftRegister with 0 delay.
if ShiftRegisters is empty, java will complain:
```
java.util.NoSuchElementException
scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150)
```
This fix this issue and return `in` directly when ShiftRegister size is 0.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
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* add ShiftRegisters to expose register inside ShiftRegister.
* use Seq.iter for oneline implementation.
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* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl.
* add scaladoc.
* add test.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Cookbook: clean up desiredName example
* Update cookbook.md
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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nitpick
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Using https://github.com/ucb-bar/chisel-repo-tools/pull/31
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* Remove space between backticks and language
* Make code examples in memories explanation work
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add documentation guide about memory initialization
* Move information to experimental and add ref
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* Add CCC2021 info
* Update README.md
* Update README.md
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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