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authorJiuyang Liu2021-03-27 03:04:51 +0000
committerGitHub2021-03-27 03:04:51 +0000
commit7b8fbbe8913a2eb92f50948dc2be50dc482fb58d (patch)
treeec6bf24320e21a71c3dff23ffecb7a2a7eabcf72
parent26461d500f402310cb3adf914b636be3a3a8e442 (diff)
CCC 2021 placeholder (#1794)
* Add CCC2021 info * Update README.md * Update README.md
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## Upcoming Events
+### Chisel Dev Meeting
Chisel/FIRRTL development meetings happen every Monday and Tuesday from 1100--1200 PT.
Call-in info and meeting notes are available [here](https://docs.google.com/document/d/1BLP2DYt59DqI-FgFCcjw8Ddl4K-WU0nHmQu0sZ_wAGo/).
+### Chisel Community Conference 2021, Shanghai, China. 6/24/2021
+The ShanghaiTech University and Institute of Software, Chinese Academy of Sciences will hold the first annual RISC-V Summit China (https://riscvsummitchina.github.io/) at the ShanghaiTech Zhangjiang campus from June 22 to 24, 2021, and the Chisel Community Conference will follow this conference from June 25 to 26, 2021.
+
+This Summit is the annual international event promoting Chisel, the new hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. This conference brings together the new experience from community and industry with tutorials, exhibitions, and more.
+
+This year’s conference program will demonstrate exciting new features of Chisel and amazing projects implemented by Chisel/FIRRTL. The call for speakers for the Chisel Summit is open from Monday, March 29 and speakers will be notified in late April or early May.
+
+CFP Link will be updated soon.
+
---
[![Join the chat at https://gitter.im/chipsalliance/chisel3](https://badges.gitter.im/chipsalliance/chisel3.svg)](https://gitter.im/chipsalliance/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)