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2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
* Add scaladoc examples for Vec and Bundle * address comments, added @example tag eliminate extraneous context * address comments, added @example tag eliminate extraneous context * ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.
2017-02-08Bump sbt version.Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
* Fix up Absolute value #abs Defines #abs in Num Implement #abs in UInt Change #abs in SInt to return an SInt Change #abs in FixedPoint to return a FixedPoint Added a couple of tests Add some scala style suppression to Bits so I can read code in IntelliJ * Per review Add tests that abs works for positive values Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec Used fixed point literals in fixed points abs definition
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
* Added vec IO tests for #104 * Added Vec test case for Reg of vecs * Change Vec creation to check if gen is lit (and hence needs to be declared) Fixes #104 * Fix tests (add IO())), Vec.fill() * Fix deprecated usage. * Add Binding IO() NPE fix so tests pass. * Fix style - use space consistently. * Fix style - use space consistently.
2017-02-03Fix potential NPE if we try to evaluate isMissingIOWrapper() inside IO(). (#479)Jim Lawson
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
* Move to cookbook * Change FSM implementation to use switch & is * Add non-FSM implementation * Add execution-driven test
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-31fix buildInfoPackage name (and comment)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
Fix default suggested name of Module instances (now based on desired name rather than actual assigned name). Remove parent/child relationship from Namespace. Previously, Module and Bundle namespaces were "children" of the Module definition namespace. This could lead to collisions that would give unexpected names for module instances or Bundle elements. In particular, otherwise identical modules that instantiate other identical modules in such a way that the instance cannot be named via reflection would not be deduplicated because the names of the instances would collide with the names of the modules in the Builder.globalNamespace.
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
2017-01-30Add shift register with reset (#439)Stevo
* [stevo]: add reset initialization to shift register * [stevo]: better comment * [stevo]: add tests, fix bug
2017-01-27Add pointer to ScalaDoc. (#397)Jim Lawson
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-27Add basic Chisel2 compatibility sanity checks. (#340)Jim Lawson
2017-01-27Have checkpoint report (and clear) non-fatal errors. (#376)Jim Lawson
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
2017-01-26Change definition of root project to minimize potential confusion.Jim Lawson
2017-01-26Use the same firrtl for all sub-projects.Jim Lawson
Use the root project's unmanagedBase (".../lib") in all sub-projects.
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
Fixing a bug in passing down execution options to firrtl
2017-01-25Better name propagation by macros (#327)Richard Lin
* Name propagation * chiselName everywhere at best-effort level * Better collision handling * Allow recursing into inner anonymous functions * Add for loop and anonymous inner function tests
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
Record gives uses the power to create collections of heterogenous elements. Bundle is a special case of Record that uses reflection to populate the elements of the collection. Bundle also attempts to implement cloneType whereas users of Record are required to supply one.
2017-01-20Mark Annotation and FixedPoint as experimental (#444)Chick Markley
* Mark Annotation and FixedPoint as experimental Fix tests and other references to these constructs * Made experimental imports more specific where possible
2017-01-13Make fromBits work with types other than UInt (#424)grebe
* Make fromBits work with types other than UInt * Oops, left in a println * Add test for truncation/expansion * Fix stuff that broke when FixedPoint fromBits PR was merged. * Use .BP shorthand added in previous PR
2017-01-11Merge pull request #391 from grebe/fixedPointFromBitsAdam Izraelevitz
Have FixedPoint use asFixedPoint in fromBits.
2017-01-11Merge branch 'master' into fixedPointFromBitsAdam Izraelevitz
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2017-01-10Merge branch 'master' into fixedPointFromBitsgrebe
2017-01-04Merge pull request #430 from ucb-bar/updatereadme426Jim Lawson
Update FIRRTL cloning instructions.
2017-01-03Update FIRRTL cloning instructions.Jim Lawson
2016-12-22Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-19Merge pull request #360 from ucb-bar/exceptionfixJim Lawson
Throw exceptions for cloneType failures - fix #358
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