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authorJack Koenig2017-01-10 17:18:09 -0800
committerGitHub2017-01-10 17:18:09 -0800
commit06df5adfd78061aa5ae7567882fb8c42d7260a46 (patch)
tree39b070505c95fd89e7a88eb64009d9b1468ef7a3
parent22b9beefd6ddc358f1573a305ed9b498634c6d23 (diff)
Make stop() immediately end simulation for Verilator tests (#434)
-rw-r--r--src/main/resources/top.cpp7
-rw-r--r--src/main/scala/chisel3/Driver.scala2
-rw-r--r--src/test/scala/chiselTests/Harness.scala5
-rw-r--r--src/test/scala/chiselTests/Stop.scala13
4 files changed, 26 insertions, 1 deletions
diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp
index 075d7085..4e9c1433 100644
--- a/src/main/resources/top.cpp
+++ b/src/main/resources/top.cpp
@@ -5,6 +5,13 @@
# include <verilated_vcd_c.h> // Trace file format header
#endif
+// Override Verilator definition so first $finish ends simulation
+// Note: VL_USER_FINISH needs to be defined when compiling Verilator code
+void vl_finish(const char* filename, int linenum, const char* hier) {
+ Verilated::flushCall();
+ exit(0);
+}
+
using namespace std;
//VGCDTester *top;
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 40c94b54..c569a81b 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -128,7 +128,7 @@ trait BackendCompilationUtilities {
s"+define+PRINTF_COND=!$topModule.reset",
s"+define+STOP_COND=!$topModule.reset",
"-CFLAGS",
- s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+ s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -DVL_USER_FINISH -include V$dutFile.h""",
"-Mdir", dir.toString,
"--exe", cppHarness.toString)
System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 83f60391..8a12cd7b 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -43,6 +43,11 @@ int main(int argc, char **argv, char **env) {
delete top;
exit(0);
}
+
+void vl_finish(const char* filename, int linenum, const char* hier) {
+ Verilated::flushCall();
+ exit(0);
+}
""", ".cpp") _
/** Compiles a C++ emulator from Verilog and returns the path to the
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 4afb077a..1c2d390d 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -10,8 +10,21 @@ class StopTester() extends BasicTester {
stop()
}
+class StopImmediatelyTester extends BasicTester {
+ val cycle = Reg(init = 0.asUInt(4.W))
+ cycle := cycle + 1.U
+ when (cycle === 4.U) {
+ stop()
+ }
+ assert(cycle =/= 5.U, "Simulation did not exit upon executing stop()")
+}
+
class StopSpec extends ChiselFlatSpec {
"stop()" should "stop and succeed the testbench" in {
assertTesterPasses { new StopTester }
}
+
+ it should "end the simulation immediately" in {
+ assertTesterPasses { new StopImmediatelyTester }
+ }
}