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AgeCommit message (Expand)Author
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Use Verilator 4.006; bump to Scala 2.12.7 (#947)Jim Lawson
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Import aliases for chisel3.core (#998)Richard Lin
2019-01-22Define Data .toString (#985)Richard Lin
2019-01-22Remove ghpages (#992)Jim Lawson
2019-01-22Merge pull request #978 from seldridge/boring-utils-dedup-fixSchuyler Eldridge
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
2019-01-18Remove bin (#991)Richard Lin
2019-01-17Merge pull request #987 from freechipsproject/unary-not-fixSchuyler Eldridge
2019-01-17Unary_- is truncatingAndrew Waterman
2019-01-17Make combinational-multiplier warning less vagueAndrew Waterman
2019-01-17Improve description of UInt.asSIntAndrew Waterman
2019-01-17Fix width-inference description of Bits.<<Andrew Waterman
2019-01-17Fix scaladoc for UInt.unary_!Andrew Waterman
2019-01-17Merge pull request #988 from freechipsproject/improve-andrSchuyler Eldridge
2019-01-17Merge branch 'master' into improve-andrSchuyler Eldridge
2019-01-17Generate better code for UInt.andRAndrew Waterman
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-11For chiselName, use nameRecursively rather than matching on HasIdAndrew Waterman
2019-01-11Move nameRecursively into Builder so it can be used elsewhereAndrew Waterman
2019-01-09Merge pull request #979 from seldridge/procedural-wire-assignmentSchuyler Eldridge
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
2019-01-07Add explicit Sonatype resolvers so SNAPSHOTs can be found remotely. (#975)Jim Lawson
2018-12-23Add Windows setup instructions to readme (#964)Richard Lin
2018-12-19Fix width inferencing issue (#952)Jack Koenig
2018-12-11Merge pull request #961 from freechipsproject/subwrapSchuyler Eldridge
2018-12-11Emit UInt.-% as tail(sub(x,y),1), not tail(asUInt(sub(x,y)),1)Andrew Waterman
2018-12-06Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue (#956)Jack Koenig
2018-12-04Merge pull request #950 from freechipsproject/as-boolsJack Koenig
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
2018-11-26Trim Stack Trace (#931)Albert Chen
2018-11-21Update description given that Chisel3 has been released (#948)edwardcwang
2018-11-21Bump sbt to 1.2.6; update dependencies (#941)Jim Lawson
2018-11-20Make Vec cloneType keep directions of elements (#945)Jack Koenig
2018-11-13Add Chisel logo to README (#935)Albert Magyar
2018-11-08Merge pull request #930 from albert-magyar/logoSchuyler Eldridge
2018-11-08Add SVG and PNG formatted Chisel logosAlbert Magyar
2018-11-05Convert to 2.1 .circleci/config.yml (#926)Jim Lawson
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