summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2021-03-11[plugin] Split ChiselComponent into its own fileJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-03Add header for chisel-enum.md (#1800)Jack Koenig
2021-03-02Adding ChiselEnum Documentation Entry (#1795)chrisbaldwin2
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-24Aggregate: fix typo (#1789)edwardcwang
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
2021-02-10Merge pull request #1624 from chipsalliance/gc-dataJack Koenig
2021-02-09Make it possible to GC Data instancesJack Koenig
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-05Add file line to source link from scaladoc (#1776)John's Brew
2021-02-04Minor docs improvements (#1774)Jack Koenig
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
2021-02-01Bump to Scala 2.12.13 (#1766)Jack Koenig
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2021-01-27Fix incorrect comment in ScalaDoc (#1756)Jack Koenig
2021-01-24Refactor EnumAnnotations and EnumFactory (#1747)SoyaOhnishi
2021-01-22Add redirect for Scala 2.11 upgrade page (#1749)Jack Koenig
2021-01-21Merge pull request #1745 from chipsalliance/remove-val-ioJack Koenig
2021-01-21Apply suggestions from code reviewJack Koenig
2021-01-21Update docs for the removal of val io and MultiIOModuleJack Koenig
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
2021-01-21Deprecate override_clock and override_reset in ModuleJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2021-01-20remove 2.11 dedicated code. (#1744)Jiuyang Liu
2021-01-20Fix Mergify condition for labeling backports (#1742)Jack Koenig
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
2021-01-15Merge pull request #1732 from chipsalliance/farewell_scala_211Jack Koenig
2021-01-15farewell Scala 2.11Jiuyang liu
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not serialize...Megan Wachs
2021-01-06Update meeting url (#1716)Jiuyang Liu
2020-12-17Automate publishing of SNAPSHOTS with sbt-ci-release (#1706)Jack Koenig
2020-12-17Remove CircleCI (#1702)Jack Koenig
2020-12-17Bump SNAPSHOT and SNAPSHOT dependencies (#1701)Jack Koenig
2020-12-16Switch to using Github Actions CI (#1690)Jack Koenig
2020-12-08Make Maven show chisel3 as apache-2.0 (#1695)Chick Markley
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message (#...Jiuyang Liu
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
2020-12-02readme: simplify sbt snippet and update to the latest stable release (#1686)Kevin Laeufer
2020-11-24Update some README links to chipsalliance (#1673)Jack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
2020-11-11Add custom mdoc modifier for emitted Verilog (#1666)Jack Koenig
2020-11-11Ignore tests using System.setSecurityManager (#1661)Jack Koenig
2020-11-11Refine autonaming to have more intuitive behavior (#1660)Jack Koenig
2020-11-05For HasId.setRef, have first set win (with force override) (#1655)Jack Koenig
2020-11-03Remove Data.setRef assertion (#1654)Jack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 15:48:39 +0000