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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update scalacheck-1-14, ... to 3.1.4.0
* Update scalacheck-1-14, ... to 3.1.4.0
* Update scalacheck-1-14 to 3.1.4.0
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add test to check ShiftRegister(s) with delay is 0.
This should break ShiftRegister(x, 0) since last is not exist in a empty
Seq. Originally, test only test 1 to 4, which missed a potential bug
from #1723.
* Fix ShiftRegister with 0 delay.
if ShiftRegisters is empty, java will complain:
```
java.util.NoSuchElementException
scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150)
```
This fix this issue and return `in` directly when ShiftRegister size is 0.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
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* add ShiftRegisters to expose register inside ShiftRegister.
* use Seq.iter for oneline implementation.
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* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl.
* add scaladoc.
* add test.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Cookbook: clean up desiredName example
* Update cookbook.md
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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nitpick
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Using https://github.com/ucb-bar/chisel-repo-tools/pull/31
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* Remove space between backticks and language
* Make code examples in memories explanation work
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add documentation guide about memory initialization
* Move information to experimental and add ref
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* Add CCC2021 info
* Update README.md
* Update README.md
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Update the FAQ and add doc on versioning
* Update modules.md
Co-authored-by: Megan Wachs <megan@sifive.com>
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Updates to chisel3 documentation for website:
* guard code examples with mdoc and fix errors encountered along the way
* move some website content here vs splitting the content across two repos
* Bring in the interval-types and loading memories content so that it will be visible from the website
* remove all references to the wiki (deprecated)
* Remove reference to Wiki from the README
* fix tabbing and compile of chisel3-vs-chisel2 section
* Appendix: faqs now guarded and compile
* FAQs: move to resources section
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Change top.cpp to deassert reset one time unit before the clock asserts.
This avoids a Verilator simultation issue in top.cpp where the eval()
function is only called once per simultation loop. If the clock and
reset are both changed and eval() is only called once, then any
combinational update due to a change in reset is not visible to the
sequential logic. This avoids issues where the downstream compilation
utilities move synchronous reset logic outside of an always block that
describes a synchronous reset flip flop.
Reset now deasserts on time unit 10 and the clock ticks on time unit
11.
h/t @albert-magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Compiler plugin implemented autoclonetype
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The compiler plugin obviates the need for using stack traces to
determine outer objects in autoclonetype. When the plugin was used to
compile a given Bundle, it will no longer collect a stack trace upon
construction. This should have massive benefits to elaboration runtime.
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