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AgeCommit message (Expand)Author
2016-07-25catch Bad connection exceptionJim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
2016-07-21Ensure test_wire is sinkable.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Compile ok.Jim Lawson
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Remove explicit literal binding.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-08For Module instances we haven't named, suggest the Module class nameAndrew Waterman
2016-06-06Merge pull request #211 from ucb-bar/front_end_dependencyJim Lawson
2016-06-06Move more publishing definitions into commonSettings.Jim Lawson
2016-06-03Merge pull request #194 from ucb-bar/front_end_dependencyJim Lawson
2016-06-03Update publishing dependenciesJim Lawson
2016-06-03Merge branch 'master' into front_end_dependencyJim Lawson
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
2016-05-31Remove unsafe implicit conversions from BitPatducky
2016-05-31Move BitPat out of core/frontend, add implicit conversionDucky
2016-05-26Fix type constraint on PriorityMuxAndrew Waterman
2016-05-20Merge pull request #186 from ucb-bar/sloc_implRichard Lin
2016-05-20Implementation of source locatorsducky
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
2016-05-18Add a hack to build.sbt to allow local publishingchick
2016-05-13Merge pull request #191 from ucb-bar/classic_tester_prep_alt2Jim Lawson
2016-05-12remove Tester.scala because chiselMain is now implemented in the chisel-teste...Danny
2016-05-11Merge pull request #184 from ucb-bar/fix-regnextColin Schmidt
2016-05-11RegNext and RegInit should match Reg(next=) and Reg(init=)Andrew Waterman
2016-05-10Some -> OptionDonggyu Kim
2016-05-10Merge pull request #181 from ucb-bar/emitRefactorJim Lawson
2016-05-10Move emit out of IRducky
2016-05-10Have Bits.toBools return Seq, not VecAndrew Waterman
2016-05-10Relax Mem write-masks to Seq, rather than VecAndrew Waterman
2016-05-10Merge pull request #178 from ucb-bar/cfr_fixJim Lawson
2016-05-09Include Chisel Frontend in JARducky
2016-05-09remove vpi source filesDonggyu Kim
2016-05-09fix width inference in enumDonggyu Kim
2016-05-09get -> getOrElseDonggyu Kim
2016-05-08Fixed sbt error where the typechecker was complaining. Just converted the Seq...azidar
2016-05-05Move Chisel API into separate chiselFrontend compilation unit in preparation ...ducky
2016-05-04Multiple assign testerducky
2016-05-04Remove dependences from Chisel core on Chisel utilsAndrew Waterman
2016-05-04Support writing literals like 1.U or -1.SAndrew Waterman
2016-05-04clock|reset to _clock|_reset, added explanatory commentStephen Twigg
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