Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3

81 files changed, 1085 insertions, 288 deletions

diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 1eef5d69..a453d5e0 100644
--- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -1,21 +1,21 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
 
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
   */
 sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   def width: Width = flatten.map(_.width).reduce(_ + _)
 }
 
@@ -163,8 +163,8 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
     Vec(length, gen).asInstanceOf[this.type]
 
   private val t = gen
-  private[Chisel] def toType: String = s"${t.toType}[$length]"
-  private[Chisel] lazy val flatten: IndexedSeq[Bits] =
+  private[chisel3] def toType: String = s"${t.toType}[$length]"
+  private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
   for ((elt, i) <- self zipWithIndex)
@@ -315,7 +315,7 @@ class Bundle extends Aggregate(NO_DIR) {
 
   /** Returns a list of elements in this Bundle.
     */
-  private[Chisel] lazy val namedElts = {
+  private[core] lazy val namedElts = {
     val nameMap = LinkedHashMap[String, Data]()
     val seen = HashSet[Data]()
     for (m <- getClass.getMethods.sortWith(_.getName < _.getName)) {
@@ -331,17 +331,17 @@ class Bundle extends Aggregate(NO_DIR) {
     }
     ArrayBuffer(nameMap.toSeq:_*) sortWith {case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))}
   }
-  private[Chisel] def toType = {
+  private[chisel3] def toType = {
     def eltPort(elt: Data): String = {
       val flipStr = if (elt.isFlip) "flip " else ""
       s"${flipStr}${elt.getRef.name} : ${elt.toType}"
     }
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
   }
-  private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
-  private[Chisel] def addElt(name: String, elt: Data): Unit =
+  private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
+  private[core] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
-  private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
+  private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
 
   override def cloneType : this.type = {
@@ -372,6 +372,6 @@ class Bundle extends Aggregate(NO_DIR) {
   }
 }
 
-private[Chisel] object Bundle {
-  val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits")
+private[core] object Bundle {
+  val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits", "newType")
 }
diff --git a/chiselFrontend/src/main/scala/Chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index 4187c579..db62f4a8 100644
--- a/chiselFrontend/src/main/scala/Chisel/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
 
 object assert { // scalastyle:ignore object.name
   /** Checks for a condition to be valid in the circuit at all times. If the
@@ -71,3 +71,17 @@ object assert { // scalastyle:ignore object.name
     Predef.assert(cond, "")
   }
 }
+
+object stop { // scalastyle:ignore object.name
+  /** Terminate execution with a failure code. */
+  def apply(code: Int)(implicit sourceInfo: SourceInfo): Unit = {
+    when (!Builder.forcedModule.reset) {
+      pushCommand(Stop(sourceInfo, Node(Builder.forcedModule.clock), code))
+    }
+  }
+
+  /** Terminate execution, indicating success. */
+  def apply()(implicit sourceInfo: SourceInfo): Unit = {
+    stop(0)
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
new file mode 100644
index 00000000..cb76159a
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -0,0 +1,190 @@
+package chisel3.core
+
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+
+/**
+* BiConnect.connect executes a bidirectional connection element-wise.
+*
+* Note that the arguments are left and right (not source and sink) so the
+* intent is for the operation to be commutative.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right (or if the right side has extra fields).
+*
+* See elemConnect for details on how the root connections are issued.
+*
+*/
+
+object BiConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class BiConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def BothDriversException =
+    BiConnectException(": Both Left and Right are drivers")
+  def NeitherDriverException =
+    BiConnectException(": Neither Left nor Right is a driver")
+  def UnknownDriverException =
+    BiConnectException(": Locally unclear whether Left or Right (both internal)")
+  def UnknownRelationException =
+    BiConnectException(": Left or Right unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    BiConnectException(": Left and Right are different length Vecs.")
+  def MissingLeftFieldException(field: String) =
+    BiConnectException(s".$field: Left Bundle missing field ($field).")
+  def MissingRightFieldException(field: String) =
+    BiConnectException(s": Right Bundle missing field ($field).")
+  def MismatchedException(left: String, right: String) =
+    BiConnectException(s": Left ($left) and Right ($right) have different types.")
+
+  /** This function is what recursively tries to connect a left and right together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, left: Data, right: Data, context_mod: Module): Unit =
+    (left, right) match {
+      // Handle element case (root case)
+      case (left_e: Element, right_e: Element) => {
+        elemConnect(sourceInfo, left_e, right_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (left_v: Vec[Data @unchecked], right_v: Vec[Data @unchecked]) => {
+        if(left_v.length != right_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until left_v.length) {
+          try {
+            connect(sourceInfo, left_v(idx), right_v(idx), context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (left_b: Bundle, right_b: Bundle) => {
+        // Verify right has no extra fields that left doesn't have
+        for((field, right_sub) <- right_b.elements) {
+          if(!left_b.elements.isDefinedAt(field)) throw MissingLeftFieldException(field)
+        }
+        // For each field in left, descend with right
+        for((field, left_sub) <- left_b.elements) {
+          try {
+            right_b.elements.get(field) match {
+              case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
+              case None => throw MissingRightFieldException(field)
+            }
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
+          }
+        }
+      }
+      // Left and right are different subtypes of Data so fail
+      case (left, right) => throw MismatchedException(left.toString, right.toString)
+    }
+
+  // These functions (finally) issue the connection operation
+  // Issue with right as sink, left as source
+  private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, right.lref, left.ref))
+  }
+  // Issue with left as sink, right as source
+  private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, left.lref, right.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, left: Element, right: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If left or right have no location, assume in context module
+    // This can occur if one of them is a literal, unbound will error previously
+    val left_mod: Module  = left.binding.location.getOrElse(context_mod)
+    val right_mod: Module = right.binding.location.getOrElse(context_mod)
+
+    val left_direction: Option[Direction] = left.binding.direction
+    val right_direction: Option[Direction] = right.binding.direction
+    // None means internal
+
+    // CASE: Context is same module as left node and right node is in a child module
+    if( (left_mod == context_mod) &&
+        (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnectL2R(left, right)
+        case (None,         Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectR2L(left, right)
+        case (None,         Some(Output)) => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Output)) => throw BothDriversException
+        case (Some(Output), Some(Input))  => throw NeitherDriverException
+        case (_,            None)         => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module as right node and left node is in child module
+    else if( (right_mod == context_mod) &&
+             (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Input),  None)         => issueConnectR2L(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Output), None)         => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Output)) => throw NeitherDriverException
+        case (Some(Output), Some(Input))  => throw BothDriversException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module that both left node and right node are in
+    else if( (context_mod == left_mod) && (context_mod == right_mod) ) {
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Input),  Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Input),  None)         => issueConnectL2R(left, right)
+        case (None,         Some(Output)) => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Output), None)         => issueConnectR2L(left, right)
+        case (None,         Some(Input))  => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Input))  => throw BothDriversException
+        case (Some(Output), Some(Output)) => throw NeitherDriverException
+        case (None,         None)         => throw UnknownDriverException
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing left node
+    //                                        and the module containing right node
+    //   Note: This includes case when left and right in same module but in parent
+    else if( (left_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (right_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Output)) => issueConnectR2L(left, right)
+        case (Some(Output), Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Input))  => throw NeitherDriverException
+        case (Some(Output), Some(Output)) => throw BothDriversException
+        case (_, None)                    => throw UnknownRelationException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
new file mode 100644
index 00000000..c7346dce
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
@@ -0,0 +1,64 @@
+package chisel3.core
+
+/**
+* A Binder is a function from UnboundBinding to some Binding.
+*
+* These are used exclusively by Binding.bind and sealed in order to keep
+* all of them in one place. There are two flavors of Binders:
+* Non-terminal (returns another UnboundBinding): These are used to reformat an
+*   UnboundBinding (like setting direction) before it is terminally bound.
+* Terminal (returns any other Binding): Due to the nature of Bindings, once a
+*   Data is bound to anything but an UnboundBinding, it is forever locked to
+*   being that type (as it now represents something in the hardware graph).
+*
+* Note that some Binders require extra arguments to be constructed, like the
+* enclosing Module.
+*/
+
+sealed trait Binder[Out <: Binding] extends Function1[UnboundBinding, Out]{
+  def apply(in: UnboundBinding): Out
+}
+
+// THE NON-TERMINAL BINDERS
+// These 'rebind' to another unbound node of different direction!
+case object InputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Input))
+}
+case object OutputBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(Some(Direction.Output))
+}
+case object FlippedBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(in.direction.map(_.flip))
+  // TODO(twigg): flipping a None should probably be a warning/error
+}
+// The need for this should be transient.
+case object NoDirectionBinder extends Binder[UnboundBinding] {
+  def apply(in: UnboundBinding) = UnboundBinding(None)
+}
+
+// THE TERMINAL BINDERS
+case object LitBinder extends Binder[LitBinding] {
+  def apply(in: UnboundBinding) = LitBinding()
+}
+
+case class MemoryPortBinder(enclosure: Module) extends Binder[MemoryPortBinding] {
+  def apply(in: UnboundBinding) = MemoryPortBinding(enclosure)
+}
+
+case class OpBinder(enclosure: Module) extends Binder[OpBinding] {
+  def apply(in: UnboundBinding) = OpBinding(enclosure)
+}
+
+// Notice how PortBinder uses the direction of the UnboundNode
+case class PortBinder(enclosure: Module) extends Binder[PortBinding] {
+  def apply(in: UnboundBinding) = PortBinding(enclosure, in.direction)
+}
+
+case class RegBinder(enclosure: Module) extends Binder[RegBinding] {
+  def apply(in: UnboundBinding) = RegBinding(enclosure)
+}
+
+case class WireBinder(enclosure: Module) extends Binder[WireBinding] {
+  def apply(in: UnboundBinding) = WireBinding(enclosure)
+}
+
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
new file mode 100644
index 00000000..d8d9ebd2
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -0,0 +1,179 @@
+package chisel3.core
+
+/**
+ * The purpose of a Binding is to indicate what type of hardware 'entity' a
+ * specific Data's leaf Elements is actually bound to. All Data starts as being
+ * Unbound (and the whole point of cloneType is to return an unbound version).
+ * Then, specific API calls take a Data, and return a bound version (either by
+ * binding the original model or cloneType then binding the clone). For example,
+ * Reg[T<:Data](...) returns a T bound to RegBinding.
+ *
+ * It is considered invariant that all Elements of a single Data are bound to
+ * the same concrete type of Binding.
+ *
+ * These bindings can be checked (e.g. checkSynthesizable) to make sure certain
+ * operations are valid. For example, arithemetic operations or connections can
+ * only be executed between synthesizable nodes. These checks are to avoid
+ * undefined reference errors.
+ *
+ * Bindings can carry information about the particular element in the graph it
+ * represents like:
+ * - For ports (and unbound), the 'direction'
+ * - For (relevant) synthesizable nodes, the enclosing Module
+ *
+ * TODO(twigg): Enrich the bindings to carry more information like the hosting
+ * module (when applicable), direction (when applicable), literal info (when
+ * applicable). Can ensure applicable data only stored on relevant nodes. e.g.
+ * literal info on LitBinding, direction info on UnboundBinding and PortBinding,
+ * etc.
+ *
+ * TODO(twigg): Currently, bindings only apply at the Element level and an
+ * Aggregate is considered bound via its elements. May be appropriate to allow
+ * Aggregates to be bound along with the Elements. However, certain literal and
+ * port direction information doesn't quite make sense in aggregates. This would
+ * elegantly handle the empty Vec or Bundle problem though.
+ *
+ * TODO(twigg): Binding is currently done via allElements. It may be more
+ * elegant if this was instead done as a more explicit tree walk as that allows
+ * for better errors.
+ */
+
+object Binding {
+  // Two bindings are 'compatible' if they are the same type.
+  // Check currently kind of weird: just ensures same class
+  private def compatible(a: Binding, b: Binding): Boolean = a.getClass == b.getClass
+  private def compatible(nodes: Seq[Binding]): Boolean =
+    if(nodes.size > 1)
+      (for((a,b) <- nodes zip nodes.tail) yield compatible(a,b))
+      .fold(true)(_&&_)
+    else true
+
+  case class BindingException(message: String) extends Exception(message)
+  def AlreadyBoundException(binding: String) = BindingException(s": Already bound to $binding")
+  def NotSynthesizableException = BindingException(s": Not bound to synthesizable node, currently only Type description")
+
+  // This recursively walks down the Data tree to look at all the leaf 'Element's
+  // Will build up an error string in case something goes wrong
+  // TODO(twigg): Make member function of Data.
+  //   Allows oddities like sample_element to be better hidden
+  private def walkToBinding(target: Data, checker: Element=>Unit): Unit = target match {
+    case (element: Element) => checker(element)
+    case (vec: Vec[Data @unchecked]) => {
+      try walkToBinding(vec.sample_element, checker)
+      catch {
+        case BindingException(message) => throw BindingException(s"(*)$message")
+      }
+      for(idx <- 0 until vec.length) {
+        try walkToBinding(vec(idx), checker)
+        catch {
+          case BindingException(message) => throw BindingException(s"($idx)$message")
+        }
+      }
+    }
+    case (bundle: Bundle) => {
+      for((field, subelem) <- bundle.elements) {
+        try walkToBinding(subelem, checker)
+        catch {
+          case BindingException(message) => throw BindingException(s".$field$message")
+        }
+      }
+    }
+  }
+
+  // Use walkToBinding to actually rebind the node type
+  def bind[T<:Data](target: T, binder: Binder[_<:Binding], error_prelude: String): target.type = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {
+          element.binding = binder(unbound)
+        }
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+    target
+  }
+
+  // Excepts if any root element is already bound
+  def checkUnbound(target: Data, error_prelude: String): Unit = {
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case unbound @ UnboundBinding(_) => {}
+        case binding => throw AlreadyBoundException(binding.toString)
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+  }
+
+  // Excepts if any root element is unbound and thus not on the hardware graph
+  def checkSynthesizable(target: Data, error_prelude: String): Unit =
+    try walkToBinding(
+      target,
+      element => element.binding match {
+        case SynthesizableBinding() => {} // OK
+        case binding => throw NotSynthesizableException
+      }
+    )
+    catch {
+      case BindingException(message) => throw BindingException(s"$error_prelude$message")
+    }
+}
+
+// Location refers to 'where' in the Module hierarchy this lives
+sealed trait Binding {
+  def location: Option[Module]
+  def direction: Option[Direction]
+}
+
+// Constrained-ness refers to whether 'bound by Module boundaries'
+// An unconstrained binding, like a literal, can be read by everyone
+sealed trait UnconstrainedBinding extends Binding {
+  def location = None
+}
+// A constrained binding can only be read/written by specific modules
+// Location will track where this Module is
+sealed trait ConstrainedBinding extends Binding {
+  def enclosure: Module
+  def location = Some(enclosure)
+}
+
+// An undirectioned binding means the element represents an internal node
+//   with no meaningful concept of a direction
+sealed trait UndirectionedBinding extends Binding { def direction = None }
+
+// This is the default binding, represents data not yet positioned in the graph
+case class UnboundBinding(direction: Option[Direction])
+    extends Binding with UnconstrainedBinding
+
+
+// A synthesizable binding is 'bound into' the hardware graph
+object SynthesizableBinding {
+  def unapply(target: Binding): Boolean = target.isInstanceOf[SynthesizableBinding]
+  // Type check OK because Binding and SynthesizableBinding is sealed
+}
+sealed trait SynthesizableBinding extends Binding
+case class LitBinding() // will eventually have literal info
+    extends SynthesizableBinding with UnconstrainedBinding with UndirectionedBinding
+
+case class MemoryPortBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
+// However, Chisel currently binds all op results to a module
+case class OpBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class PortBinding(enclosure: Module, direction: Option[Direction])
+    extends SynthesizableBinding with ConstrainedBinding
+
+case class RegBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
+
+case class WireBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index bc8cc8e2..e6a4be71 100644
--- a/chiselFrontend/src/main/scala/Chisel/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushOp
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
+import chisel3.internal._
+import chisel3.internal.Builder.pushOp
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
   UIntTransform, MuxTransform}
-import firrtl.PrimOp._
+import chisel3.internal.firrtl.PrimOp._
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
@@ -25,9 +25,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[Chisel] def fromInt(x: BigInt, w: Int): this.type
+  private[chisel3] def fromInt(x: BigInt, w: Int): this.type
 
-  private[Chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
+  private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
 
@@ -118,16 +118,16 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt =
     apply(x.toInt, y.toInt)
 
-  private[Chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
+  private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other)))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref))
 
-  private[Chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
+  private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
-  private[Chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
+  private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref))
 
   /** Returns this wire zero padded up to the specified width.
@@ -356,13 +356,13 @@ abstract trait Num[T <: Data] {
 /** A data type for unsigned integers, represented as a binary bitvector.
   * Defines arithmetic operations between other integer types.
   */
-sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULit] = None)
+sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit] = None)
     extends Bits(dir, width, lit) with Num[UInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[core] override def cloneTypeWidth(w: Width): this.type =
     new UInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"UInt$width"
+  private[core] def toType = s"UInt$width"
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     UInt(value, width).asInstanceOf[this.type]
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
@@ -482,7 +482,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[Chisel] sealed trait UIntFactory {
+private[core] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(NO_DIR, Width())
   /** Create a UInt type or port with fixed width. */
@@ -535,16 +535,16 @@ object UInt extends UIntFactory
 
 sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None)
     extends Bits(dir, width, lit) with Num[SInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[core] override def cloneTypeWidth(w: Width): this.type =
     new SInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"SInt$width"
+  private[chisel3] def toType = s"SInt$width"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: SInt => this connect that
     case _ => this badConnect that
   }
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     SInt(value, width).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
@@ -666,12 +666,12 @@ object SInt {
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
 sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type = {
+  private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
     new Bool(dir).asInstanceOf[this.type]
   }
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = {
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
     Bool(value == 1).asInstanceOf[this.type]
   }
diff --git a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index b634f021..f2d9558d 100644
--- a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.{ModuleIO, DefInvalid}
-import internal.sourceinfo.SourceInfo
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
@@ -24,23 +24,31 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[Chisel] def ports = io.elements.toSeq
+  override private[core] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[Chisel] def setRefs(): this.type = {
-    for ((name, port) <- ports) {
-      port.setRef(ModuleIO(this, _namespace.name(name)))
-    }
+  override private[core] def setRefs(): this.type = {
     // setRef is not called on the actual io.
     // There is a risk of user improperly attempting to connect directly with io
     // Long term solution will be to define BlackBox IO differently as part of
     //   it not descending from the (current) Module
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+    // We need to call forceName and onModuleClose on all of the sub-elements
+    // of the io bundle, but NOT on the io bundle itself.
+    // Doing so would cause the wrong names to be assigned, since their parent
+    // is now the module itself instead of the io bundle.
+    for (id <- _ids; if id ne io) {
+      id.forceName(default="T", _namespace)
+      id._onModuleClose
+    }
     this
   }
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index d16843f7..fcdc86bb 100644
--- a/chiselFrontend/src/main/scala/Chisel/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -38,9 +38,9 @@ abstract class Data(dirArg: Direction) extends HasId {
   // Sucks this is mutable state, but cloneType doesn't take a Direction arg
   private var isFlipVar = dirArg == INPUT
   private var dirVar = dirArg
-  private[Chisel] def isFlip = isFlipVar
+  private[core] def isFlip = isFlipVar
 
-  private[Chisel] def overrideDirection(newDir: Direction => Direction,
+  private[core] def overrideDirection(newDir: Direction => Direction,
                                         newFlip: Boolean => Boolean): this.type = {
     this.isFlipVar = newFlip(this.isFlipVar)
     for (field <- this.flatten)
@@ -51,16 +51,16 @@ abstract class Data(dirArg: Direction) extends HasId {
   def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
   def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
 
-  private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[Chisel] def lref: Node = Node(this)
-  private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
-  private[Chisel] def cloneTypeWidth(width: Width): this.type
-  private[Chisel] def toType: String
+  private[core] def lref: Node = Node(this)
+  private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
+  private[core] def cloneTypeWidth(width: Width): this.type
+  private[chisel3] def toType: String
 
   def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
 
@@ -71,7 +71,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
 
-  def width: Width
+  private[core] def width: Width
   final def getWidth: Int = width.get
 
   // While this being in the Data API doesn't really make sense (should be in
@@ -83,7 +83,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   // currently don't exist (while this information may be available during
   // FIRRTL emission, it would break directionality querying from Chisel, which
   // does get used).
-  private[Chisel] def flatten: IndexedSeq[Bits]
+  private[chisel3] def flatten: IndexedSeq[Bits]
 
   /** Creates an new instance of this type, unpacking the input Bits into
     * structured data.
@@ -150,9 +150,9 @@ object Clock {
 // TODO: Document this.
 sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
   def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
-  private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[Chisel] def toType = "Clock"
+  private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel3] def toType = "Clock"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: Clock => this connect that
diff --git a/chiselFrontend/src/main/scala/Chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index e34d5499..38f5ef14 100644
--- a/chiselFrontend/src/main/scala/Chisel/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
 
 object Mem {
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
diff --git a/chiselFrontend/src/main/scala/Chisel/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 4fba6b25..40102cd6 100644
--- a/chiselFrontend/src/main/scala/Chisel/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -1,16 +1,16 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.Builder.dynamicContext
-import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
-import internal.firrtl
-import internal.firrtl.{Command, Component, DefInstance, DefInvalid, ModuleIO}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.{Command, Component, DefInstance, DefInvalid, ModuleIO}
+import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -59,7 +59,7 @@ extends HasId {
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
   // This function binds the iodef as a port in the hardware graph
-  private[Chisel] def Port[T<:Data](iodef: T): iodef.type = {
+  private[chisel3] def Port[T<:Data](iodef: T): iodef.type = {
     // Bind each element of the iodef to being a Port
     Binding.bind(iodef, PortBinder(this), "Error: iodef")
     iodef
@@ -89,9 +89,9 @@ extends HasId {
     Port(iodef)
   }
 
-  private[Chisel] val _namespace = Builder.globalNamespace.child
-  private[Chisel] val _commands = ArrayBuffer[Command]()
-  private[Chisel] val _ids = ArrayBuffer[HasId]()
+  private[core] val _namespace = Builder.globalNamespace.child
+  private[chisel3] val _commands = ArrayBuffer[Command]()
+  private[code] val _ids = ArrayBuffer[HasId]()
   Builder.currentModule = Some(this)
 
   /** Name of the instance. */
@@ -104,13 +104,13 @@ extends HasId {
   val clock = Port(Input(Clock()))
   val reset = Port(Input(Bool()))
 
-  private[Chisel] def addId(d: HasId) { _ids += d }
+  private[chisel3] def addId(d: HasId) { _ids += d }
 
-  private[Chisel] def ports: Seq[(String,Data)] = Vector(
+  private[core] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[Chisel] def computePorts: Seq[firrtl.Port] =
+  private[core] def computePorts: Seq[firrtl.Port] =
     for((name, port) <- ports) yield {
       // Port definitions need to know input or output at top-level.
       // By FIRRTL semantics, 'flipped' becomes an Input
@@ -118,7 +118,7 @@ extends HasId {
       firrtl.Port(port, direction)
     }
 
-  private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+  private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
       case Some(p) => {
         pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
@@ -130,7 +130,7 @@ extends HasId {
     }
   }
 
-  private[Chisel] def setRefs(): this.type = {
+  private[core] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
new file mode 100644
index 00000000..64c71cb2
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -0,0 +1,172 @@
+package chisel3.core
+
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.Connect
+import scala.language.experimental.macros
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+
+/**
+* MonoConnect.connect executes a mono-directional connection element-wise.
+*
+* Note that this isn't commutative. There is an explicit source and sink
+* already determined before this function is called.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right. The right side is allowed to have extra Bundle fields.
+* Vecs must still be exactly the same size.
+*
+* See elemConnect for details on how the root connections are issued.
+*
+* Note that a valid sink must be writable so, one of these must hold:
+* - Is an internal writable node (Reg or Wire)
+* - Is an output of the current module
+* - Is an input of a submodule of the current module
+*
+* Note that a valid source must be readable so, one of these must hold:
+* - Is an internal readable node (Reg, Wire, Op)
+* - Is a literal
+* - Is a port of the current module or submodule of the current module
+*/
+
+object MonoConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class MonoConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def UnreadableSourceException =
+    MonoConnectException(": Source is unreadable from current module.")
+  def UnwritableSinkException =
+    MonoConnectException(": Sink is unwriteable by current module.")
+  def UnknownRelationException =
+    MonoConnectException(": Sink or source unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    MonoConnectException(": Sink and Source are different length Vecs.")
+  def MissingFieldException(field: String) =
+    MonoConnectException(s": Source Bundle missing field ($field).")
+  def MismatchedException(sink: String, source: String) =
+    MonoConnectException(s": Sink ($sink) and Source ($source) have different types.")
+
+  /** This function is what recursively tries to connect a sink and source together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, sink: Data, source: Data, context_mod: Module): Unit =
+    (sink, source) match {
+      // Handle element case (root case)
+      case (sink_e: Element, source_e: Element) => {
+        elemConnect(sourceInfo, sink_e, source_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) => {
+        if(sink_v.length != source_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until sink_v.length) {
+          try {
+            connect(sourceInfo, sink_v(idx), source_v(idx), context_mod)
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (sink_b: Bundle, source_b: Bundle) => {
+        // For each field, descend with right
+        for((field, sink_sub) <- sink_b.elements) {
+          try {
+            source_b.elements.get(field) match {
+              case Some(source_sub) => connect(sourceInfo, sink_sub, source_sub, context_mod)
+              case None => throw MissingFieldException(field)
+            }
+          } catch {
+            case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
+          }
+        }
+      }
+      // Sink and source are different subtypes of data so fail
+      case (sink, source) => throw MismatchedException(sink.toString, source.toString)
+    }
+
+  // This function (finally) issues the connection operation
+  private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, sink.lref, source.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, sink: Element, source: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If source has no location, assume in context module
+    // This can occur if is a literal, unbound will error previously
+    val sink_mod: Module   = sink.binding.location.getOrElse(throw UnwritableSinkException)
+    val source_mod: Module = source.binding.location.getOrElse(context_mod)
+
+    val sink_direction: Option[Direction] = sink.binding.direction
+    val source_direction: Option[Direction] = source.binding.direction
+    // None means internal
+
+    // CASE: Context is same module that both left node and right node are in
+    if( (context_mod == sink_mod) && (context_mod == source_mod) ) {
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Output), _) => issueConnect(sink, source)
+        case (None,         _) => issueConnect(sink, source)
+        case (Some(Input),  _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as sink node and right node is in a child module
+    else if( (sink_mod == context_mod) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CURRENT MOD   CHILD MOD
+        case (None,         Some(Output)) => issueConnect(sink, source)
+        case (None,         Some(Input))  => issueConnect(sink, source)
+        case (Some(Output), Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), Some(Input))  => issueConnect(sink, source)
+        case (_,            None) => throw UnreadableSourceException
+        case (Some(Input),  _)    => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is same module as source node and sink node is in child module
+    else if( (source_mod == context_mod) &&
+             (sink_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  _) => issueConnect(sink, source)
+        case (Some(Output), _) => throw UnwritableSinkException
+        case (None,         _) => throw UnwritableSinkException
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing sink node
+    //                                        and the module containing source node
+    //   Note: This includes case when sink and source in same module but in parent
+    else if( (sink_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (source_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction
+      (sink_direction, source_direction) match {
+        //    SINK          SOURCE
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnect(sink, source)
+        case (Some(Input),  Some(Output)) => issueConnect(sink, source)
+        case (Some(Output), _)            => throw UnwritableSinkException
+        case (_,            None)         => throw UnreadableSourceException
+        case (None,         _)            => throw UnwritableSinkException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index cc121eac..400c144d 100644
--- a/chiselFrontend/src/main/scala/Chisel/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
 
 object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
@@ -29,7 +29,7 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+  private[core] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
     val clock = Builder.forcedModule.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }
diff --git a/chiselFrontend/src/main/scala/Chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index c8faa5c9..14ae9650 100644
--- a/chiselFrontend/src/main/scala/Chisel/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -1,14 +1,15 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
-  private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
+  private[core] def makeType[T <: Data](t: T = null, next: T = null,
+init: T = null): T = {
     if (t ne null) {
       t.cloneType
     } else if (next ne null) {
diff --git a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 9a15fd5f..91cb9e89 100644
--- a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -1,12 +1,12 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
-private[Chisel] object SeqUtils {
+private[chisel3] object SeqUtils {
   /** Equivalent to Cat(r(n-1), ..., r(0)) */
   def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg
 
diff --git a/chiselFrontend/src/main/scala/Chisel/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 90b3d1a5..196e7903 100644
--- a/chiselFrontend/src/main/scala/Chisel/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo}
 
 object when {  // scalastyle:ignore object.name
   /** Create a `when` condition block, where whether a block of logic is
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index fddc4bd7..e5b85736 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -1,29 +1,35 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel3.internal
 
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
-import Chisel._
-import Chisel.internal.firrtl._
+import chisel3._
+import core._
+import firrtl._
 
-private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
-  private var i = 0L
-  private val names = collection.mutable.HashSet[String]()
+private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+  private val names = collection.mutable.HashMap[String, Long]()
+  for (keyword <- keywords)
+    names(keyword) = 1
 
-  private def rename(n: String) = { i += 1; s"${n}_${i}" }
+  private def rename(n: String): String = {
+    val index = names.getOrElse(n, 1L)
+    val tryName = s"${n}_${index}"
+    names(n) = index + 1
+    if (this contains tryName) rename(n) else tryName
+  }
 
   def contains(elem: String): Boolean = {
-    keywords.contains(elem) || names.contains(elem) ||
-      parent.map(_ contains elem).getOrElse(false)
+    names.contains(elem) || parent.map(_ contains elem).getOrElse(false)
   }
 
   def name(elem: String): String = {
     if (this contains elem) {
       name(rename(elem))
     } else {
-      names += elem
+      names(elem) = 1
       elem
     }
   }
@@ -32,7 +38,7 @@ private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]
   def child: Namespace = child(Set())
 }
 
-private[Chisel] class IdGen {
+private[chisel3] class IdGen {
   private var counter = -1L
   def next: Long = {
     counter += 1
@@ -40,12 +46,12 @@ private[Chisel] class IdGen {
   }
 }
 
-private[Chisel] trait HasId {
-  private[Chisel] def _onModuleClose: Unit = {} // scalastyle:ignore method.name
-  private[Chisel] val _parent: Option[Module] = Builder.currentModule
+private[chisel3] trait HasId {
+  private[chisel3] def _onModuleClose: Unit = {} // scalastyle:ignore method.name
+  private[chisel3] val _parent: Option[Module] = Builder.currentModule
   _parent.foreach(_.addId(this))
 
-  private[Chisel] val _id: Long = Builder.idGen.next
+  private[chisel3] val _id: Long = Builder.idGen.next
   override def hashCode: Int = _id.toInt
   override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
@@ -62,12 +68,12 @@ private[Chisel] trait HasId {
     for(hook <- postname_hooks) { hook(name) }
     this
   }
-  private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+  private[chisel3] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
 
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Bundle)
-  private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit =
+  private[chisel3] def forceName(default: =>String, namespace: Namespace): Unit =
     if(_ref.isEmpty) {
       val candidate_name = suggested_name.getOrElse(default)
       val available_name = namespace.name(candidate_name)
@@ -75,14 +81,14 @@ private[Chisel] trait HasId {
     }
 
   private var _ref: Option[Arg] = None
-  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
-  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
-  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
-  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
-  private[Chisel] def getRef: Arg = _ref.get
+  private[chisel3] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[chisel3] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[chisel3] def getRef: Arg = _ref.get
 }
 
-private[Chisel] class DynamicContext {
+private[chisel3] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
@@ -90,7 +96,7 @@ private[Chisel] class DynamicContext {
   val errors = new ErrorLog
 }
 
-private[Chisel] object Builder {
+private[chisel3] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
   private def dynamicContext: DynamicContext =
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index 6c4c0880..7ae0580f 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -1,20 +1,20 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel3.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import Chisel._
+import chisel3.core._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private[Chisel] object throwException {
+private[chisel3] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private[Chisel] class ErrorLog {
+private[chisel3] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index 66bfc7a4..5e3bf33e 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -12,7 +12,7 @@
 // writers to append source locator information at the point of a library
 // function invocation.
 
-package Chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -42,7 +42,7 @@ object SourceInfoMacro {
   def generate_source_info(c: Context): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
-    q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+    q"_root_.chisel3.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 62784cee..64d7d5fd 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal._
-import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+package chisel3.internal.firrtl
+
+import chisel3._
+import core._
+import chisel3.internal._
+import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
 case class PrimOp(val name: String) {
   override def toString: String = name
@@ -53,8 +55,8 @@ case class Node(id: HasId) extends Arg {
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[Chisel] def forcedWidth = widthArg.known
-  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  private[chisel3] def forcedWidth = widthArg.known
+  private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
 
   protected def minWidth: Int
   if (forcedWidth) {
diff --git a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 82ad5b9e..ba14b78f 100644
--- a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -3,7 +3,7 @@
 // This file transform macro definitions to explicitly add implicit source info to Chisel method
 // calls.
 
-package Chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -23,7 +23,7 @@ trait SourceInfoTransformMacro {
   val c: Context
   import c.universe._
   def thisObj = c.prefix.tree
-  def implicitSourceInfo = q"implicitly[_root_.Chisel.internal.sourceinfo.SourceInfo]"
+  def implicitSourceInfo = q"implicitly[_root_.chisel3.internal.sourceinfo.SourceInfo]"
 }
 
 class WireTransform(val c: Context) extends SourceInfoTransformMacro {
diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/Chisel/package.scala
deleted file mode 100644
index f05e8b5d..00000000
--- a/src/main/scala/Chisel/package.scala
+++ /dev/null
@@ -1,31 +0,0 @@
-package object Chisel {
-  import scala.language.experimental.macros
-  
-  import internal.firrtl.Width
-  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())
-    def S: SInt = SInt(x, Width())
-  }
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())
-    def S: SInt = SInt(BigInt(x), Width())
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)
-  }
-  
-  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
-    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-  
-    def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
-    def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
-    def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
-  }
-}
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 02204684..0979314f 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3
 
 import scala.sys.process._
 import java.io._
@@ -71,6 +71,7 @@ trait BackendCompilationUtilities {
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
         s"+define+PRINTF_COND=!$topModule.reset",
+        s"+define+STOP_COND=!$topModule.reset",
         "-CFLAGS",
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
index 575ae138..cd47c731 100644
--- a/src/main/scala/Chisel/FileSystemUtilities.scala
+++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
+
+import chisel3._
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
index a72debc3..a41599a3 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/chisel3/compatibility/Main.scala
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
 
 import java.io.File
 
+import chisel3._
+
 @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
   def apply[T <: Module](args: Array[String], gen: () => T): Unit =
     Predef.assert(false, "No more chiselMain in Chisel3")
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
index 702884aa..3e8b33e6 100644
--- a/src/main/scala/Chisel/throwException.scala
+++ b/src/main/scala/chisel3/compatibility/throwException.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
+
+import chisel3._
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
 @throws(classOf[Exception])
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 7ca3268a..08646cf9 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+package chisel3.internal.firrtl
+import chisel3._
+import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
-private[Chisel] object Emitter {
+private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
 }
 
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
new file mode 100644
index 00000000..35bbd1c4
--- /dev/null
+++ b/src/main/scala/chisel3/package.scala
@@ -0,0 +1,107 @@
+package object chisel3 {
+  import scala.language.experimental.macros
+
+  import internal.firrtl.Width
+  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+  
+  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+    def U: UInt = UInt(x, Width())
+    def S: SInt = SInt(x, Width())
+
+  import util.BitPat
+
+
+  type Direction = chisel3.core.Direction
+  type Data = chisel3.core.Data
+  val Wire = chisel3.core.Wire
+  val Clock = chisel3.core.Clock
+  type Clock = chisel3.core.Clock
+
+  type Aggregate = chisel3.core.Aggregate
+  val Vec = chisel3.core.Vec
+  type Vec[T <: Data] = chisel3.core.Vec[T]
+  type VecLike[T <: Data] = chisel3.core.VecLike[T]
+  type Bundle = chisel3.core.Bundle
+
+  val assert = chisel3.core.assert
+
+  type Element = chisel3.core.Element
+  type Bits = chisel3.core.Bits
+  val Bits = chisel3.core.Bits
+  type Num[T <: Data] = chisel3.core.Num[T]
+  type UInt = chisel3.core.UInt
+  val UInt = chisel3.core.UInt
+  type SInt = chisel3.core.SInt
+  val SInt = chisel3.core.SInt
+  type Bool = chisel3.core.Bool
+  val Bool = chisel3.core.Bool
+  val Mux = chisel3.core.Mux
+
+  type BlackBox = chisel3.core.BlackBox
+
+  val Mem = chisel3.core.Mem
+  type MemBase[T <: Data] = chisel3.core.MemBase[T]
+  type Mem[T <: Data] = chisel3.core.Mem[T]
+  val SeqMem = chisel3.core.SeqMem
+  type SeqMem[T <: Data] = chisel3.core.SeqMem[T]
+
+  val Module = chisel3.core.Module
+  type Module = chisel3.core.Module
+
+  val printf = chisel3.core.printf
+
+  val Reg = chisel3.core.Reg
+
+  val when = chisel3.core.when
+  type WhenContext = chisel3.core.WhenContext
+
+  /**
+  * These implicit classes allow one to convert scala.Int|scala.BigInt to
+  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+  * mark a width for the new literal.
+  *
+  * Also provides .asBool to scala.Boolean and .asUInt to String
+  *
+  * Note that, for stylistic reasons, one hould avoid extracting immediately
+  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+  * Prefer storing the result and then extracting from it.
+  */
+  implicit class addLiteraltoScalaInt(val target: Int) extends AnyVal {
+    def asUInt() = UInt.Lit(target)
+    def asSInt() = SInt.Lit(target)
+    def asUInt(width: Int) = UInt.Lit(target, width)
+    def asSInt(width: Int) = SInt.Lit(target, width)
+
+    // These were recently added to chisel2/3 but are not to be used internally
+    @deprecated("asUInt should be used over U", "gchisel")
+    def U() = UInt.Lit(target)
+    @deprecated("asSInt should be used over S", "gchisel")
+    def S() = SInt.Lit(target)
+    @deprecated("asUInt should be used over U", "gchisel")
+    def U(width: Int) = UInt.Lit(target, width)
+    @deprecated("asSInt should be used over S", "gchisel")
+    def S(width: Int) = SInt.Lit(target, width)
+  }
+  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+    def U: UInt = UInt(BigInt(x), Width())
+    def S: SInt = SInt(BigInt(x), Width())
+  }
+  implicit class fromStringToLiteral(val x: String) extends AnyVal {
+    def U: UInt = UInt(x)
+  }
+  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
+    def B: Bool = Bool(x)
+  }
+  
+  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
+    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+
+    def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
+    def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
+    def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
+  }
+}
diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 94113836..329237c6 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel3.testers
+import chisel3._
 
 import scala.language.experimental.macros
 
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index a56bb8b7..586fa780 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel3.testers
+
+import chisel3._
 import scala.io.Source
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 5cef4b24..a5397682 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -3,7 +3,9 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 96206f63..9eb5cf67 100644
--- a/src/main/scala/Chisel/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -1,10 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
 
 import scala.language.experimental.macros
 
-import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 239a295e..ab1ff550 100644
--- a/src/main/scala/Chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -3,7 +3,10 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 object FillInterleaved
 {
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index dd706e62..469bf9ab 100644
--- a/src/main/scala/Chisel/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -1,6 +1,9 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 06cab903..1174c71c 100644
--- a/src/main/scala/Chisel/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -3,7 +3,9 @@
 /** Circuit-land math operations.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 9cab25ef..6218feb0 100644
--- a/src/main/scala/Chisel/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -3,13 +3,15 @@
 /** Conditional blocks.
   */
 
-package Chisel
+package chisel3.util
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
 import scala.reflect.runtime.universe._
 import scala.reflect.macros.blackbox._
 
+import chisel3._
+
 /** This is identical to [[Chisel.when when]] with the condition inverted */
 object unless {  // scalastyle:ignore object.name
   def apply(c: Bool)(block: => Unit) {
@@ -59,7 +61,9 @@ object switch {  // scalastyle:ignore object.name
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val sc = c.universe.internal.reificationSupport.freshTermName("sc")
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
-      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      // TODO: remove when Chisel compatibility package is removed
+      case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel3.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 872e830a..40615769 100644
--- a/src/main/scala/Chisel/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 66b348e0..73f58ed4 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -3,7 +3,9 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 20057197..4ecc243b 100644
--- a/src/main/scala/Chisel/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -3,7 +3,9 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 6a230022..4d816a19 100644
--- a/src/main/scala/Chisel/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object ImplicitConversions {
   implicit def intToUInt(x: Int): UInt = UInt(x)
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index 839b1d1f..a30c276f 100644
--- a/src/main/scala/Chisel/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -3,7 +3,9 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
index 54922fc4..9e909c0c 100644
--- a/src/main/scala/Chisel/util/Lookup.scala
+++ b/src/main/scala/chisel3/util/Lookup.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 5f8212d8..73665f0f 100644
--- a/src/main/scala/Chisel/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -3,7 +3,9 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 9d92321a..9956a7e3 100644
--- a/src/main/scala/Chisel/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -3,7 +3,10 @@
 /** Mux circuit generators.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
@@ -37,7 +40,7 @@ object MuxLookup {
     * @param mapping a sequence to search of keys and values
     * @return the value found or the default if not
     */
-  def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = {
+  def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = {
     var res = default
     for ((k, v) <- mapping.reverse)
       res = Mux(k === key, v, res)
@@ -51,7 +54,7 @@ object MuxCase {
   /** @param default the default value if none are enabled
     * @param mapping a set of data values with associated enables
     * @return the first value in mapping that is enabled */
-  def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = {
+  def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
     var res = default
     for ((t, v) <- mapping.reverse){
       res = Mux(t, v, res)
diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 73f27403..820c72d6 100644
--- a/src/main/scala/Chisel/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -3,7 +3,9 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 6584a4bf..81de4754 100644
--- a/src/main/scala/Chisel/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -3,7 +3,9 @@
 /** Variations and helpers for registers.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object RegNext {
 
diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
index ec5a11cc..f36f926f 100644
--- a/src/main/scala/Chisel/util/TransitName.scala
+++ b/src/main/scala/chisel3/util/TransitName.scala
@@ -1,5 +1,6 @@
-package Chisel
+package chisel3.util
 
+import chisel3._
 import internal.HasId
 
 object TransitName {
diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 38997cab..4078a76a 100644
--- a/src/main/scala/Chisel/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -3,7 +3,9 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An Bundle containing data and a signal determining if it is valid */
 class Valid[+T <: Data](gen: T) extends Bundle
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 750ed6e4..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 19aa956c..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 5877149f..c1154883 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -4,8 +4,10 @@ package chiselTests
 
 import java.io.File
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class BlackBoxInverter extends BlackBox {
   val io = IO(new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 147575e1..029407dd 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
   val x = UInt(width = 32)
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index da68b0cb..d335bdf6 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -6,8 +6,8 @@ import java.io.File
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel._
-import Chisel.testers._
+import chisel3._
+import chisel3.testers._
 
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners extends Assertions {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 58f26c1f..e5d1fbea 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -1,11 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 07a76cdc..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -1,10 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 07622667..4a872245 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -1,11 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 38e00690..770d2e0e 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 28b00adb..682103f7 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 11e8b70b..26af944f 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index edb8c80f..a8b907af 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index bc838766..83f60391 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -1,13 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel.testers.BasicTester
+
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
 
 class HarnessSpec extends ChiselPropSpec
-  with Chisel.BackendCompilationUtilities {
+  with chisel3.BackendCompilationUtilities {
 
   def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 54144bea..2d5e7f3e 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -1,8 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LFSR16 extends Module {
   val io = IO(new Bundle {
@@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 }
 */
 
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index a321522b..770be326 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index ba251916..7c0bc40e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt(32))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 1e5ee798..b22b2820 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2f464123..d5e9b998 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -3,29 +3,31 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
   val test = Wire(UInt(width=4))
-  assert(test === UInt(7))  // allow read references before assign references
+  assert(test === UInt.Lit(7))  // allow read references before assign references
 
-  test := UInt(13)
-  assert(test === UInt(7))  // output value should be position-independent
+  test := UInt.Lit(13)
+  assert(test === UInt.Lit(7))  // output value should be position-independent
 
-  test := UInt(7)
-  assert(test === UInt(7))  // this obviously should work
+  test := UInt.Lit(7)
+  assert(test === UInt.Lit(7))  // this obviously should work
 
-  when(cnt.value === UInt(1)) {
+  when(cnt.value === UInt.Lit(1)) {
     stop()
   }
 }
 
 class ReassignmentTester() extends BasicTester {
-  val test = UInt(15)
-  test := UInt(7)
+  val test = UInt.Lit(15)
+  test := UInt.Lit(7)
 }
 
 class MultiAssignSpec extends ChiselFlatSpec {
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index ad694925..8e4c7579 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 1f33f8ab..6c92e87b 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class Padder extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index f682f310..14b21631 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index eb8b4b25..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
   val x = UInt(254)
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index f2620d88..391dd7de 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.core.DataMirror
+import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 670aa703..fafec95a 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class Risc extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 934c66a4..a98edf9b 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 46e5dc23..683c5224 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -1,8 +1,11 @@
 // See LICENSE for license details.
 
 package chiselTests
+
 import scala.collection.mutable.Stack
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class ChiselStack(val depth: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 878f090c..4afb077a 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class StopTester() extends BasicTester {
   stop()
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 751dc127..6ebe0875 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 3c57daae..2f3e9368 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 4e8506cf..ca83ee1d 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -1,9 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 import org.scalatest._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 5239c6ba..b90c1f09 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 936541c0..081990ad 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 5baff275..00b1e7de 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class VendingMachine extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index a6572706..5f3d3e61 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -3,8 +3,10 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)