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AgeCommit message (Expand)Author
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
2021-07-28Just install z3 from apt-get in CI (#2056)Jack Koenig
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
2021-07-27Clarify test dependencies in README, add noplugin (#2053)Megan Wachs
2021-07-23Update sbt-mdoc to 2.2.22 (#2047)Scala Steward
2021-07-22MovingAverage3 => MovingSum3 (#2050)Jack Koenig
2021-07-14Fix Cat rename signal (#2011)Leway Colin
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
2021-07-13Merge pull request #2041 from chipsalliance/ci_testJiuyang Liu
2021-07-13fix ci, add more matrix.Jiuyang Liu
2021-07-13fix for GitHub Action missing ivy FIRRTL.Jiuyang Liu
2021-07-13refactor github actionJiuyang Liu
2021-07-12Update sbt to 1.5.5Scala Steward
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
2021-07-08Update docs on dontTouch as optimization barrier (#2015)Schuyler Eldridge
2021-07-07Fix ChiselEnum docs (#2016)Jack Koenig
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Merge pull request #1999 from chipsalliance/fix-chiselenum-warningsJack Koenig
2021-07-01Update docs for ChiselEnumJack Koenig
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
2021-07-01Change Chisel warnings to use logger instead of printlnJack Koenig
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Merge pull request #1993 from chipsalliance/fix-select-clonemoduleasrecordJack Koenig
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-29updated readme to mention verilator dependency (#1984)anniej-sifive
2021-06-29deprecate getPorts with modulePorts. (#1945)Jiuyang Liu
2021-06-28Merge pull request #1974 from chipsalliance/fix-clonemoduleasrecord-totargetJack Koenig
2021-06-28Set refs for ModuleClone and ClonePorts in less hacky wayJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-28CCC update (#1982)Jiuyang Liu
2021-06-28Add link to Chisel Breakdown slides to README (#1979)Jack Koenig
2021-06-25Update type_hierarchy (#1977)Jack Koenig
2021-06-25Correct typos in core/src/main/scala/chisel3/Num.scala (#1976)Felix Yan
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-06-23CCC info update (#1969)Jiuyang Liu
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
2021-06-21Switch to Github Actions CI Badge (#1967)Jack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16Update sbt-buildinfo to 0.10.0 (#1545)Scala Steward
2021-06-16Update sbt to 1.5.4 (#1960)Scala Steward
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
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