| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-03-11 | Import memory files inline for Verilog generation (#1805) | Carlos Eduardo | |
| This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument. | |||
| 2020-11-11 | Add custom mdoc modifier for emitted Verilog (#1666) | Jack Koenig | |
| 2020-08-21 | Added website docs and mdoc. (#1560) | Adam Izraelevitz | |
| * Added website docs and mdoc. Removed all warnings * Updated README and added build to circle ci * Added how to build documentation, deprecated wiki * Fix copypasta Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2020-02-13 | Fix mill build (#1324) | Sequencer | |
| * add mill build * add gitignore and mill version | |||
| 2019-01-18 | Remove bin (#991) | Richard Lin | |
| 2018-07-05 | Ignore eclipse temporaries | Richard Lin | |
| 2018-06-29 | Add Emacs temporaries, backups to .gitignore (#837) | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2017-12-14 | Fix a few compiler warnings (#738) | Jack Koenig | |
| Make InvalidateAPI emit to a test directory Add *.swp and test_run_dir to .gitignore | |||
| 2016-10-28 | Add firrtl.jar to .gitignore | Andrew Waterman | |
| 2016-02-24 | changing build.sbt to prepare for chisel3 distribution | chick | |
| copied machinery from chisel2 build.sbt added a few intellij lines to gitignore | |||
| 2015-12-15 | Fix some nits: add that line to .gitignore that keeps coming back, do ↵ | ducky | |
| parallel testing by default | |||
| 2015-07-24 | Use CHISEL_BIN, CX, generalize generated/targetDir, convert filter to ↵ | Jim Lawson | |
| python, cd into targetDir before launching simulator (via Driver). | |||
 |
index : chiselX | |
| Chisel with SFC compatibility |
| summaryrefslogtreecommitdiff |
path: root/.gitignore