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-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 0793fd7d..3fb18893 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -39,10 +39,7 @@ private class Emitter(circuit: Circuit) {
unindent()
s"skip"
}
- e.sourceInfo match {
- case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}]"
- case _: NoSourceInfo => firrtlLine
- }
+ firrtlLine + e.sourceInfo.makeMessage(" " + _)
}
// Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.