3 files changed, 40 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 41cfbec4..5a3b43e6 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -614,4 +614,26 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate(new MyModule)
   }
 
+  behavior.of("BlackBox")
+
+  it should "have invalidated ports in a compatibility context" in {
+    class ExtModuleInvalidatedTester extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(8.W))
+        val out = Output(UInt(8.W))
+      })
+      val inst = Module(new BlackBox {
+        val io = IO(new Bundle {
+          val in = Input(UInt(8.W))
+          val out = Output(UInt(8.W))
+        })
+      })
+      inst.io.in := io.in
+      io.out := inst.io.out
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new ExtModuleInvalidatedTester)
+    chirrtl should include("inst.in is invalid")
+    chirrtl should include("inst.out is invalid")
+  }
 }
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index b5a8ff7c..3ab4cc32 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -88,6 +88,17 @@ class ExtModuleWithFlatIOTester extends Module {
   io <> inst.badIO
 }
 
+class ExtModuleInvalidatedTester extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+  val inst = Module(new ExtModule {
+    val in = IO(Input(UInt(8.W)))
+    val out = IO(Output(UInt(8.W)))
+  })
+  inst.in := in
+  out := inst.out
+}
+
 class ExtModuleSpec extends ChiselFlatSpec {
   "A ExtModule inverter" should "work" in {
     assertTesterPasses({ new ExtModuleTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly)
@@ -117,4 +128,10 @@ class ExtModuleSpec extends ChiselFlatSpec {
     chirrtl should include("inst.in <= io.in")
     chirrtl shouldNot include("badIO")
   }
+
+  it should "not have invalidated ports in a chisel3._ context" in {
+    val chirrtl = ChiselStage.emitChirrtl(new ExtModuleInvalidatedTester)
+    chirrtl shouldNot include("inst.in is invalid")
+    chirrtl shouldNot include("inst.out is invalid")
+  }
 }
diff --git a/src/test/scala/chiselTests/aop/InjectionSpec.scala b/src/test/scala/chiselTests/aop/InjectionSpec.scala
index 9b29b0ba..1b69efa3 100644
--- a/src/test/scala/chiselTests/aop/InjectionSpec.scala
+++ b/src/test/scala/chiselTests/aop/InjectionSpec.scala
@@ -108,6 +108,7 @@ class InjectionSpec extends ChiselFlatSpec with Utils {
     { _: SubmoduleManipulationTester =>
       // By creating a second SubmoduleA, the module names would conflict unless they were uniquified
       val moduleSubmoduleC = Module(new SubmoduleC)
+      moduleSubmoduleC.io <> DontCare
       //if we're here then we've elaborated correctly
       stop()
     }