1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 4588abe1..55d58d77 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -27,6 +27,14 @@ trait ChiselRunners extends Assertions {
     assert(!runTester(t, additionalVResources))
   }
   def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
+
+  /** Given a generator, return the Firrtl that it generates.
+    *
+    * @param t Module generator
+    * @return Firrtl representation as a String
+    */
+  def generateFirrtl(t: => Module): String = Driver.emit(() => t)
+
   /** Compiles a Chisel Module to Verilog */
   def compile(t: => Module): String = {
     val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions