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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/Driver.scala | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index f3ba6534..d138bf1f 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -95,6 +95,18 @@ object Driver extends BackendCompilationUtilities { def emit[T <: RawModule](ir: Circuit): String = Emitter.emit(ir) + /** Elaborates the Module specified in the gen function into Verilog + * + * @param gen a function that creates a Module hierarchy + * @return the resulting String containing the design in Verilog + */ + def emitVerilog[T <: RawModule](gen: => T): String = { + execute(Array[String](), { () => gen }) match { + case ChiselExecutionSuccess(_, _, Some(firrtl.FirrtlExecutionSuccess(_, verilog))) => verilog + case _ => sys.error("Cannot get Verilog!") + } + } + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { val f = optName.getOrElse(new File(ir.name + ".fir")) val w = new FileWriter(f) |